Commit 94cb1285 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Modified pulse counting process to use a Flancter based counter which is able to…

Modified pulse counting process to use a Flancter based counter which is able to count very fast pulses
parent a7f5275f
......@@ -142,6 +142,8 @@ entity conv_common_gw is
-- Pulse I/O
pulse_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_ttl_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_blo_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_o : out std_logic_vector(g_nr_chans-1 downto 0);
-- Inverted pulse I/O
......@@ -385,6 +387,8 @@ architecture arch of conv_common_gw is
signal pulse_cnt : t_pulse_cnt;
signal ttl_pulse_cnt : t_pulse_cnt;
signal blo_pulse_cnt : t_pulse_cnt;
signal ttl_pulse_c : t_pulse_cnt;
signal blo_pulse_c : t_pulse_cnt;
signal ch_ttl_pcr : t_ch_pcr;
signal ch_ttl_pcr_ld : std_logic_vector(c_max_nr_chans-1 downto 0);
signal ch_blo_pcr : t_ch_pcr;
......@@ -465,15 +469,21 @@ architecture arch of conv_common_gw is
signal temper : std_logic_vector(15 downto 0);
--Chipscope signals
-- signal CONTROL : std_logic_vector(35 downto 0);
-- signal CLK : std_logic;
-- signal TRIG0 : std_logic_vector(7 downto 0);
-- signal TRIG1 : std_logic_vector(7 downto 0);
-- signal TRIG2 : std_logic_vector(7 downto 0);
-- signal TRIG3 : std_logic_vector(7 downto 0);
-- signal TRIG4 : std_logic_vector(7 downto 0);
-- signal TRIG5 : std_logic_vector(7 downto 0);
---------------------------------------------------------------------------------------------------
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0_in : std_logic_vector(7 downto 0);
signal TRIG1_in : std_logic_vector(7 downto 0);
signal TRIG2_in : std_logic_vector(7 downto 0);
signal TRIG3_in : std_logic_vector(7 downto 0);
signal TRIG4_in : std_logic_vector(7 downto 0);
signal TRIG5_in : std_logic_vector(7 downto 0);
-- signal TRIG6_in : std_logic_vector(7 downto 0);
-- signal TRIG7_in : std_logic_vector(7 downto 0);
-- signal TRIG8_in : std_logic_vector(7 downto 0);
-- signal TRIG9_in : std_logic_vector(7 downto 0);
-- signal TRIG10_in : std_logic_vector(7 downto 0);
-- signal TRIG11_in : std_logic_vector(7 downto 0);
--==============================================================================
-- architecture begin
......@@ -483,26 +493,28 @@ begin
---------------------------------------------------------------------------------------------------
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_20_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3,
-- TRIG4 => TRIG4,
-- TRIG5 => TRIG5);
-- chipscope_icon_1 : chipscope_icon
-- port map ( CONTROL0 => CONTROL);
-- TRIG0(7 downto 0) <= std_logic_vector(temp_rise_c_sh (7 downto 0));
-- TRIG0(7 downto 0) <= std_logic_vector(temp_rise_c_sh (15 downto 8));
-- TRIG0(7 downto 0) <= std_logic_vector(temp_rise_c_sh (23 downto 16));
-- TRIG0(7 downto 0) <= std_logic_vector(temp_rise_c_sh (31 downto 24));
-- TRIG0(7 downto 0) <= std_logic_vector(temp_rise_c_sh (39 downto 32));
-- TRIG0(7 downto 0) <= std_logic_vector(temp_rise_c_sh (7 downto 0));
chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL,
CLK => clk_20_i,
TRIG0 => TRIG0_in,
TRIG1 => TRIG1_in,
TRIG2 => TRIG2_in,
TRIG3 => TRIG3_in,
TRIG4 => TRIG4_in,
TRIG5 => TRIG5_in);
chipscope_icon_1 : chipscope_icon
port map ( CONTROL0 => CONTROL);
TRIG0_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(7 downto 0));
TRIG1_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(15 downto 8));
TRIG2_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(23 downto 16));
TRIG3_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(31 downto 24));
TRIG4_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(39 downto 32));
TRIG5_in(5 downto 0) <= pulse_outp_err_lg_p;
--============================================================================
-- Differential input buffer for 125 MHz clock
--============================================================================
......@@ -529,7 +541,7 @@ begin
generic map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => 2*(10**6)
g_reset_time => 2*(10**4)
)
port map
(
......@@ -621,7 +633,7 @@ end generate gen_no_man_trig;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
gen_pulse_chan_logic : for i in 0 to 5 generate --g_nr_chans-1 generate
gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
-- Synchronize the asynchronous trigger input into the 20 MHz clock
-- domain before passing it to the glitch filter
......@@ -685,29 +697,53 @@ gen_pulse_chan_logic : for i in 0 to 5 generate --g_nr_chans-1 generate
--------------------------------------------------------------------------------
gen_pulse_cnt : if (g_with_pulse_cnt = true) generate
cmp_pulse_cnt_ttl: fastevent_counter
port map(
sysclk_i => clk_20_i,
rstcount_i => rst_20,
en_i => '1',
trig_i => pulse_ttl_i(i),
count_int_o => ttl_pulse_c(i)
);
cmp_pulse_cnt_blo: fastevent_counter
port map(
sysclk_i => clk_20_i,
rstcount_i => rst_20,
en_i => '1',
trig_i => pulse_blo_i(i),
count_int_o => blo_pulse_c(i)
);
-- First, the pulse counters for the used channels (up to g_nr_chans)
p_pulse_cnt : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
pulse_cnt(i) <= (others => '0');
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
pulse_cnt(i) <= (others => '0');
ttl_pulse_cnt(i) <= (others => '0');
blo_pulse_cnt(i) <= (others => '0');
elsif (ch_ttl_pcr_ld(i) = '1') then
elsif (ch_ttl_pcr_ld(i) = '1') then
ttl_pulse_cnt(i) <= unsigned(ch_ttl_pcr(i));
elsif (ch_blo_pcr_ld(i) = '1') then
elsif (ch_blo_pcr_ld(i) = '1') then
blo_pulse_cnt(i) <= unsigned(ch_blo_pcr(i));
elsif (trig_chan_redge_p(i) = '1') then
pulse_cnt(i) <= pulse_cnt(i) + 1;
if (trig_chan_ttl_redge_p(i) = '1') then
ttl_pulse_cnt(i) <= ttl_pulse_cnt(i) + 1;
elsif (trig_chan_blo_redge_p(i) = '1') then
blo_pulse_cnt(i) <= blo_pulse_cnt(i) + 1;
end if;
end if;
else
ttl_pulse_cnt(i) <= ttl_pulse_c(i);
blo_pulse_cnt(i) <= blo_pulse_c(i);
-- if (trig_chan_redge_p(i) = '1') then
-- pulse_cnt(i) <= pulse_cnt(i) + 1;
-- if (trig_chan_ttl_redge_p(i) = '1') then
-- ttl_pulse_cnt(i) <= ttl_pulse_cnt(i) + 1;
-- elsif (trig_chan_blo_redge_p(i) = '1') then
-- blo_pulse_cnt(i) <= blo_pulse_cnt(i) + 1;
-- end if;
end if;
end if;
end process p_pulse_cnt;
--------------------------------------------------------------------------------
-- Connect pulse counter values for unused channels to all zeroes
gen_pulse_cnt_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
......
......@@ -146,6 +146,8 @@ package conv_common_gw_pkg is
-- Pulse inputs
pulse_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_ttl_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_blo_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_o : out std_logic_vector(g_nr_chans-1 downto 0);
-- Channel leds
......@@ -252,6 +254,19 @@ package conv_common_gw_pkg is
);
end component conv_reset_gen;
------------------------------------------------------------------------------
-- Pulse counter - Used for scenarios where clocks are shorter than the time it takes to synchronise them (Normally it taked 3 clk cycles to synchronise trigger edge.)
------------------------------------------------------------------------------
component fastevent_counter is
port (sysclk_i : in std_logic;
rstcount_i : in std_logic;
en_i : in std_logic;
trig_i : in std_logic;
count_o : out std_logic_vector(31 downto 0);
count_int_o: out unsigned(31 downto 0));
end component;
------------------------------------------------------------------------------
-- Pulse generator with optional configurable pulse width
------------------------------------------------------------------------------
......@@ -711,15 +726,7 @@ END component chipscope_ila;
component chipscope_icon IS
port (
CONTROL0: inout std_logic_vector(35 downto 0);
TDO_OUT: out std_logic;
TDI_IN: in std_logic;
RESET_IN: in std_logic;
SHIFT_IN: in std_logic;
UPDATE_IN: in std_logic;
CAPTURE_IN: in std_logic;
SEL_IN: in std_logic;
DRCK_IN: in std_logic);
CONTROL0: inout std_logic_vector(35 downto 0));
END component chipscope_icon;
end package conv_common_gw_pkg;
......
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