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level-conversion
conv-common-gw
Commits
21f76124
Commit
21f76124
authored
Aug 22, 2014
by
Theodor-Adrian Stana
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Add simulation model for conv_man_trig
parent
183c2bae
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5 changed files
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1555 additions
and
0 deletions
+1555
-0
Makefile
sim/conv_man_trig/Makefile
+1200
-0
Manifest.py
sim/conv_man_trig/Manifest.py
+8
-0
run.do
sim/conv_man_trig/run.do
+10
-0
testbench.vhd
sim/conv_man_trig/testbench.vhd
+286
-0
wave.do
sim/conv_man_trig/wave.do
+51
-0
No files found.
sim/conv_man_trig/Makefile
0 → 100644
View file @
21f76124
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
/opt/modelsim_10.0d/modeltech
VCOM_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VSIM_FLAGS
:=
VLOG_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VERILOG_SRC
:=
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
\
VERILOG_OBJ
:=
work/sockit_owm/.sockit_owm_v
\
work/spi_clgen/.spi_clgen_v
\
work/spi_shift/.spi_shift_v
\
work/spi_top/.spi_top_v
\
work/lm32_allprofiles/.lm32_allprofiles_v
\
work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v
\
work/jtag_cores/.jtag_cores_v
\
work/lm32_adder/.lm32_adder_v
\
work/lm32_addsub/.lm32_addsub_v
\
work/lm32_logic_op/.lm32_logic_op_v
\
work/lm32_shifter/.lm32_shifter_v
\
work/lm32_multiplier/.lm32_multiplier_v
\
work/jtag_tap/.jtag_tap_v
\
VHDL_SRC
:=
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
\
../../modules/conv_regs.vhd
\
../../modules/conv_pulse_gen.vhd
\
../../modules/conv_man_trig.vhd
\
../../modules/conv_ring_buf.vhd
\
../../modules/conv_pulse_timetag.vhd
\
../../modules/conv_reset_gen.vhd
\
../../top/conv_common_gw_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
\
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
\
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
\
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
\
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
\
../../ip_cores/general-cores/modules/common/gc_reset.vhd
\
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
\
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
\
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
\
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
\
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
\
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
\
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd
\
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd
\
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
\
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd
\
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd
\
../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd
\
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd
\
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd
\
../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd
\
testbench.vhd
\
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
\
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
\
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd
\
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd
\
../../top/conv_common_gw.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
\
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
\
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd
\
VHDL_OBJ
:=
work/genram_pkg/.genram_pkg_vhd
\
work/wishbone_pkg/.wishbone_pkg_vhd
\
work/gencores_pkg/.gencores_pkg_vhd
\
work/conv_regs/.conv_regs_vhd
\
work/conv_pulse_gen/.conv_pulse_gen_vhd
\
work/conv_man_trig/.conv_man_trig_vhd
\
work/conv_ring_buf/.conv_ring_buf_vhd
\
work/conv_pulse_timetag/.conv_pulse_timetag_vhd
\
work/conv_reset_gen/.conv_reset_gen_vhd
\
work/conv_common_gw_pkg/.conv_common_gw_pkg_vhd
\
work/gc_crc_gen/.gc_crc_gen_vhd
\
work/gc_moving_average/.gc_moving_average_vhd
\
work/gc_extend_pulse/.gc_extend_pulse_vhd
\
work/gc_delay_gen/.gc_delay_gen_vhd
\
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd
\
work/gc_reset/.gc_reset_vhd
\
work/gc_serial_dac/.gc_serial_dac_vhd
\
work/gc_sync_ffs/.gc_sync_ffs_vhd
\
work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd
\
work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd
\
work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2_vhd
\
work/gc_frequency_meter/.gc_frequency_meter_vhd
\
work/gc_rr_arbiter/.gc_rr_arbiter_vhd
\
work/gc_prio_encoder/.gc_prio_encoder_vhd
\
work/gc_word_packer/.gc_word_packer_vhd
\
work/gc_i2c_slave/.gc_i2c_slave_vhd
\
work/gc_glitch_filt/.gc_glitch_filt_vhd
\
work/gc_dyn_glitch_filt/.gc_dyn_glitch_filt_vhd
\
work/gc_big_adder/.gc_big_adder_vhd
\
work/gc_fsm_watchdog/.gc_fsm_watchdog_vhd
\
work/gc_bicolor_led_ctrl/.gc_bicolor_led_ctrl_vhd
\
work/testbench/.testbench_vhd
\
work/memory_loader_pkg/.memory_loader_pkg_vhd
\
work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd
\
work/inferred_sync_fifo/.inferred_sync_fifo_vhd
\
work/inferred_async_fifo/.inferred_async_fifo_vhd
\
work/conv_common_gw/.conv_common_gw_vhd
\
work/generic_dpram/.generic_dpram_vhd
\
work/generic_dpram_sameclock/.generic_dpram_sameclock_vhd
\
work/generic_dpram_dualclock/.generic_dpram_dualclock_vhd
\
work/generic_simple_dpram/.generic_simple_dpram_vhd
\
work/generic_spram/.generic_spram_vhd
\
work/gc_shiftreg/.gc_shiftreg_vhd
\
work/generic_async_fifo/.generic_async_fifo_vhd
\
work/generic_sync_fifo/.generic_sync_fifo_vhd
\
work/wb_async_bridge/.wb_async_bridge_vhd
\
work/xwb_async_bridge/.xwb_async_bridge_vhd
\
work/wb_onewire_master/.wb_onewire_master_vhd
\
work/xwb_onewire_master/.xwb_onewire_master_vhd
\
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd
\
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd
\
work/i2c_master_top/.i2c_master_top_vhd
\
work/wb_i2c_master/.wb_i2c_master_vhd
\
work/xwb_i2c_master/.xwb_i2c_master_vhd
\
work/xwb_bus_fanout/.xwb_bus_fanout_vhd
\
work/xwb_dpram/.xwb_dpram_vhd
\
work/wb_gpio_port/.wb_gpio_port_vhd
\
work/xwb_gpio_port/.xwb_gpio_port_vhd
\
work/wb_tics/.wb_tics_vhd
\
work/xwb_tics/.xwb_tics_vhd
\
work/uart_async_rx/.uart_async_rx_vhd
\
work/uart_async_tx/.uart_async_tx_vhd
\
work/uart_baud_gen/.uart_baud_gen_vhd
\
work/simple_uart_pkg/.simple_uart_pkg_vhd
\
work/simple_uart_wb/.simple_uart_wb_vhd
\
work/wb_simple_uart/.wb_simple_uart_vhd
\
work/xwb_simple_uart/.xwb_simple_uart_vhd
\
work/vic_prio_enc/.vic_prio_enc_vhd
\
work/wbgen2_pkg/.wbgen2_pkg_vhd
\
work/wb_vic/.wb_vic_vhd
\
work/xwb_vic/.xwb_vic_vhd
\
work/wb_spi/.wb_spi_vhd
\
work/xwb_spi/.xwb_spi_vhd
\
work/sdb_rom/.sdb_rom_vhd
\
work/xwb_crossbar/.xwb_crossbar_vhd
\
work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd
\
work/xwb_register_link/.xwb_register_link_vhd
\
work/wb_irq_pkg/.wb_irq_pkg_vhd
\
work/irqm_core/.irqm_core_vhd
\
work/wb_irq_lm32/.wb_irq_lm32_vhd
\
work/wb_irq_slave/.wb_irq_slave_vhd
\
work/wb_irq_master/.wb_irq_master_vhd
\
work/wb_irq_timer/.wb_irq_timer_vhd
\
work/xwb_lm32/.xwb_lm32_vhd
\
work/lm32_dp_ram/.lm32_dp_ram_vhd
\
work/lm32_ram/.lm32_ram_vhd
\
work/wb_slave_adapter/.wb_slave_adapter_vhd
\
work/xwb_clock_crossing/.xwb_clock_crossing_vhd
\
work/xwb_dma/.xwb_dma_vhd
\
work/xwb_streamer/.xwb_streamer_vhd
\
work/wb_serial_lcd/.wb_serial_lcd_vhd
\
work/wb_spi_flash/.wb_spi_flash_vhd
\
work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg_vhd
\
work/simple_pwm_wb/.simple_pwm_wb_vhd
\
work/wb_simple_pwm/.wb_simple_pwm_vhd
\
work/xwb_simple_pwm/.xwb_simple_pwm_vhd
\
work/wb_i2c_bridge/.wb_i2c_bridge_vhd
\
work/wbgen2_dpssram/.wbgen2_dpssram_vhd
\
work/wbgen2_eic/.wbgen2_eic_vhd
\
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd
\
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd
\
work/wb_slave_vic/.wb_slave_vic_vhd
\
work/xloader_registers_pkg/.xloader_registers_pkg_vhd
\
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd
\
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd
\
work/xloader_wb/.xloader_wb_vhd
\
work/spi_master/.spi_master_vhd
\
work/multiboot_fsm/.multiboot_fsm_vhd
\
work/multiboot_regs/.multiboot_regs_vhd
\
work/xwb_xil_multiboot/.xwb_xil_multiboot_vhd
\
LIBS
:=
work
LIB_IND
:=
work/.work
## rules #################################
sim
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
$(VHDL_OBJ)
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
clean
:
rm
-rf
./modelsim.ini
$(LIBS)
.PHONY
:
clean
work/.work
:
(
vlib work
&&
vmap
-modelsimini
modelsim.ini work
&&
touch
work/.work
)||
rm
-rf
work
work/sockit_owm/.sockit_owm_v
:
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/spi_clgen/.spi_clgen_v
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/spi_shift/.spi_shift_v
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/spi_top/.spi_top_v
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_allprofiles/.lm32_allprofiles_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/jtag_cores/.jtag_cores_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_adder/.lm32_adder_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_addsub/.lm32_addsub_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_logic_op/.lm32_logic_op_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_shifter/.lm32_shifter_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_multiplier/.lm32_multiplier_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/jtag_tap/.jtag_tap_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/genram_pkg/.genram_pkg_vhd
:
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wishbone_pkg/.wishbone_pkg_vhd
:
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wishbone_pkg/.wishbone_pkg
:
\
work/genram_pkg/.genram_pkg
work/gencores_pkg/.gencores_pkg_vhd
:
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gencores_pkg/.gencores_pkg
:
\
work/genram_pkg/.genram_pkg
work/conv_regs/.conv_regs_vhd
:
../../modules/conv_regs.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/conv_pulse_gen/.conv_pulse_gen_vhd
:
../../modules/conv_pulse_gen.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/conv_man_trig/.conv_man_trig_vhd
:
../../modules/conv_man_trig.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/conv_man_trig/.conv_man_trig
:
\
work/genram_pkg/.genram_pkg
work/conv_ring_buf/.conv_ring_buf_vhd
:
../../modules/conv_ring_buf.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/conv_ring_buf/.conv_ring_buf
:
\
work/genram_pkg/.genram_pkg
work/conv_pulse_timetag/.conv_pulse_timetag_vhd
:
../../modules/conv_pulse_timetag.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/conv_pulse_timetag/.conv_pulse_timetag
:
\
work/gencores_pkg/.gencores_pkg
work/conv_reset_gen/.conv_reset_gen_vhd
:
../../modules/conv_reset_gen.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/conv_common_gw_pkg/.conv_common_gw_pkg_vhd
:
../../top/conv_common_gw_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/conv_common_gw_pkg/.conv_common_gw_pkg
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/genram_pkg/.genram_pkg
work/gc_crc_gen/.gc_crc_gen_vhd
:
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_crc_gen/.gc_crc_gen
:
\
work/gencores_pkg/.gencores_pkg
work/gc_moving_average/.gc_moving_average_vhd
:
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_moving_average/.gc_moving_average
:
\
work/gencores_pkg/.gencores_pkg
work/gc_extend_pulse/.gc_extend_pulse_vhd
:
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_extend_pulse/.gc_extend_pulse
:
\
work/genram_pkg/.genram_pkg
\
work/gencores_pkg/.gencores_pkg
work/gc_delay_gen/.gc_delay_gen_vhd
:
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_delay_gen/.gc_delay_gen
:
\
work/gencores_pkg/.gencores_pkg
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd
:
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_dual_pi_controller/.gc_dual_pi_controller
:
\
work/gencores_pkg/.gencores_pkg
work/gc_reset/.gc_reset_vhd
:
../../ip_cores/general-cores/modules/common/gc_reset.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_serial_dac/.gc_serial_dac_vhd
:
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_sync_ffs/.gc_sync_ffs_vhd
:
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd
:
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_arbitrated_mux/.gc_arbitrated_mux
:
\
work/genram_pkg/.genram_pkg
\
work/gencores_pkg/.gencores_pkg
work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd
:
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_pulse_synchronizer/.gc_pulse_synchronizer
:
\
work/gencores_pkg/.gencores_pkg
work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2_vhd
:
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2
:
\
work/gencores_pkg/.gencores_pkg
work/gc_frequency_meter/.gc_frequency_meter_vhd
:
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_frequency_meter/.gc_frequency_meter
:
\
work/gencores_pkg/.gencores_pkg
work/gc_rr_arbiter/.gc_rr_arbiter_vhd
:
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_prio_encoder/.gc_prio_encoder_vhd
:
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_word_packer/.gc_word_packer_vhd
:
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_word_packer/.gc_word_packer
:
\
work/genram_pkg/.genram_pkg
work/gc_i2c_slave/.gc_i2c_slave_vhd
:
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_i2c_slave/.gc_i2c_slave
:
\
work/gencores_pkg/.gencores_pkg
work/gc_glitch_filt/.gc_glitch_filt_vhd
:
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_glitch_filt/.gc_glitch_filt
:
\
work/gencores_pkg/.gencores_pkg
work/gc_dyn_glitch_filt/.gc_dyn_glitch_filt_vhd
:
../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_dyn_glitch_filt/.gc_dyn_glitch_filt
:
\
work/gencores_pkg/.gencores_pkg
work/gc_big_adder/.gc_big_adder_vhd
:
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_big_adder/.gc_big_adder
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
work/gc_fsm_watchdog/.gc_fsm_watchdog_vhd
:
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_fsm_watchdog/.gc_fsm_watchdog
:
\
work/genram_pkg/.genram_pkg
work/gc_bicolor_led_ctrl/.gc_bicolor_led_ctrl_vhd
:
../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_bicolor_led_ctrl/.gc_bicolor_led_ctrl
:
\
work/gencores_pkg/.gencores_pkg
work/testbench/.testbench_vhd
:
testbench.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/testbench/.testbench
:
\
work/genram_pkg/.genram_pkg
work/memory_loader_pkg/.memory_loader_pkg_vhd
:
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/memory_loader_pkg/.memory_loader_pkg
:
\
work/genram_pkg/.genram_pkg
work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd
:
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_shiftreg_fifo/.generic_shiftreg_fifo
:
\
work/genram_pkg/.genram_pkg
work/inferred_sync_fifo/.inferred_sync_fifo_vhd
:
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/inferred_sync_fifo/.inferred_sync_fifo
:
\
work/genram_pkg/.genram_pkg
work/inferred_async_fifo/.inferred_async_fifo_vhd
:
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/inferred_async_fifo/.inferred_async_fifo
:
\
work/genram_pkg/.genram_pkg
work/conv_common_gw/.conv_common_gw_vhd
:
../../top/conv_common_gw.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/conv_common_gw/.conv_common_gw
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/conv_common_gw_pkg/.conv_common_gw_pkg
\
work/genram_pkg/.genram_pkg
\
work/gencores_pkg/.gencores_pkg
work/generic_dpram/.generic_dpram_vhd
:
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_dpram/.generic_dpram
:
\
work/memory_loader_pkg/.memory_loader_pkg
\
work/genram_pkg/.genram_pkg
work/generic_dpram_sameclock/.generic_dpram_sameclock_vhd
:
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_dpram_sameclock/.generic_dpram_sameclock
:
\
work/memory_loader_pkg/.memory_loader_pkg
\
work/genram_pkg/.genram_pkg
work/generic_dpram_dualclock/.generic_dpram_dualclock_vhd
:
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_dpram_dualclock/.generic_dpram_dualclock
:
\
work/memory_loader_pkg/.memory_loader_pkg
\
work/genram_pkg/.genram_pkg
work/generic_simple_dpram/.generic_simple_dpram_vhd
:
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_simple_dpram/.generic_simple_dpram
:
\
work/memory_loader_pkg/.memory_loader_pkg
\
work/genram_pkg/.genram_pkg
work/generic_spram/.generic_spram_vhd
:
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_spram/.generic_spram
:
\
work/genram_pkg/.genram_pkg
work/gc_shiftreg/.gc_shiftreg_vhd
:
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_shiftreg/.gc_shiftreg
:
\
work/genram_pkg/.genram_pkg
work/generic_async_fifo/.generic_async_fifo_vhd
:
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_async_fifo/.generic_async_fifo
:
\
work/genram_pkg/.genram_pkg
work/generic_sync_fifo/.generic_sync_fifo_vhd
:
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_sync_fifo/.generic_sync_fifo
:
\
work/genram_pkg/.genram_pkg
work/wb_async_bridge/.wb_async_bridge_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_async_bridge/.wb_async_bridge
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
work/xwb_async_bridge/.xwb_async_bridge_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_async_bridge/.xwb_async_bridge
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_onewire_master/.wb_onewire_master_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_onewire_master/.wb_onewire_master
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
work/xwb_onewire_master/.xwb_onewire_master_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_onewire_master/.xwb_onewire_master
:
\
work/wishbone_pkg/.wishbone_pkg
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/i2c_master_top/.i2c_master_top_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_i2c_master/.wb_i2c_master_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_i2c_master/.wb_i2c_master
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_i2c_master/.xwb_i2c_master_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_i2c_master/.xwb_i2c_master
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_bus_fanout/.xwb_bus_fanout_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_bus_fanout/.xwb_bus_fanout
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_dpram/.xwb_dpram_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_dpram/.xwb_dpram
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/genram_pkg/.genram_pkg
work/wb_gpio_port/.wb_gpio_port_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_gpio_port/.wb_gpio_port
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
work/xwb_gpio_port/.xwb_gpio_port_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_gpio_port/.xwb_gpio_port
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_tics/.wb_tics_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_tics/.wb_tics
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_tics/.xwb_tics_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_tics/.xwb_tics
:
\
work/wishbone_pkg/.wishbone_pkg
work/uart_async_rx/.uart_async_rx_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/uart_async_tx/.uart_async_tx_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/uart_baud_gen/.uart_baud_gen_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/simple_uart_pkg/.simple_uart_pkg_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/simple_uart_wb/.simple_uart_wb_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/simple_uart_wb/.simple_uart_wb
:
\
work/simple_uart_pkg/.simple_uart_pkg
work/wb_simple_uart/.wb_simple_uart_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_simple_uart/.wb_simple_uart
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/simple_uart_pkg/.simple_uart_pkg
\
work/genram_pkg/.genram_pkg
work/xwb_simple_uart/.xwb_simple_uart_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_simple_uart/.xwb_simple_uart
:
\
work/wishbone_pkg/.wishbone_pkg
work/vic_prio_enc/.vic_prio_enc_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_pkg/.wbgen2_pkg_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_vic/.wb_vic_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_vic/.wb_vic
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/genram_pkg/.genram_pkg
work/xwb_vic/.xwb_vic_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_vic/.xwb_vic
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_spi/.wb_spi_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_spi/.wb_spi
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_spi/.xwb_spi_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_spi/.xwb_spi
:
\
work/wishbone_pkg/.wishbone_pkg
work/sdb_rom/.sdb_rom_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/sdb_rom/.sdb_rom
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_crossbar/.xwb_crossbar_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_crossbar/.xwb_crossbar
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_sdb_crossbar/.xwb_sdb_crossbar
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_register_link/.xwb_register_link_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_register_link/.xwb_register_link
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_irq_pkg/.wb_irq_pkg_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_irq_pkg/.wb_irq_pkg
:
\
work/wishbone_pkg/.wishbone_pkg
work/irqm_core/.irqm_core_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/irqm_core/.irqm_core
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/wb_irq_pkg/.wb_irq_pkg
\
work/genram_pkg/.genram_pkg
work/wb_irq_lm32/.wb_irq_lm32_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_irq_lm32/.wb_irq_lm32
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/wb_irq_pkg/.wb_irq_pkg
work/wb_irq_slave/.wb_irq_slave_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_irq_slave/.wb_irq_slave
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/wb_irq_pkg/.wb_irq_pkg
\
work/genram_pkg/.genram_pkg
work/wb_irq_master/.wb_irq_master_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_irq_master/.wb_irq_master
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/wb_irq_pkg/.wb_irq_pkg
\
work/genram_pkg/.genram_pkg
work/wb_irq_timer/.wb_irq_timer_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_irq_timer/.wb_irq_timer
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/wb_irq_pkg/.wb_irq_pkg
\
work/genram_pkg/.genram_pkg
\
work/gencores_pkg/.gencores_pkg
work/xwb_lm32/.xwb_lm32_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_lm32/.xwb_lm32
:
\
work/wishbone_pkg/.wishbone_pkg
work/lm32_dp_ram/.lm32_dp_ram_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_dp_ram/.lm32_dp_ram
:
\
work/genram_pkg/.genram_pkg
work/lm32_ram/.lm32_ram_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_ram/.lm32_ram
:
\
work/genram_pkg/.genram_pkg
work/wb_slave_adapter/.wb_slave_adapter_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_slave_adapter/.wb_slave_adapter
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_clock_crossing/.xwb_clock_crossing_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_clock_crossing/.xwb_clock_crossing
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/genram_pkg/.genram_pkg
work/xwb_dma/.xwb_dma_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_dma/.xwb_dma
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/genram_pkg/.genram_pkg
work/xwb_streamer/.xwb_streamer_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_streamer/.xwb_streamer
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_serial_lcd/.wb_serial_lcd_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_serial_lcd/.wb_serial_lcd
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/genram_pkg/.genram_pkg
work/wb_spi_flash/.wb_spi_flash_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_spi_flash/.wb_spi_flash
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/genram_pkg/.genram_pkg
\
work/gencores_pkg/.gencores_pkg
work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/simple_pwm_wb/.simple_pwm_wb_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/simple_pwm_wb/.simple_pwm_wb
:
\
work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg
work/wb_simple_pwm/.wb_simple_pwm_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_simple_pwm/.wb_simple_pwm
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg
work/xwb_simple_pwm/.xwb_simple_pwm_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_simple_pwm/.xwb_simple_pwm
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_i2c_bridge/.wb_i2c_bridge_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_i2c_bridge/.wb_i2c_bridge
:
\
work/gencores_pkg/.gencores_pkg
work/wbgen2_dpssram/.wbgen2_dpssram_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_dpssram/.wbgen2_dpssram
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_eic/.wbgen2_eic_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_eic/.wbgen2_eic
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_fifo_async/.wbgen2_fifo_async
:
\
work/wbgen2_pkg/.wbgen2_pkg
\
work/genram_pkg/.genram_pkg
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_fifo_sync/.wbgen2_fifo_sync
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/wb_slave_vic/.wb_slave_vic_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_slave_vic/.wb_slave_vic
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/xloader_registers_pkg/.xloader_registers_pkg_vhd
:
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xloader_registers_pkg/.xloader_registers_pkg
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd
:
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd
:
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/xloader_registers_pkg/.xloader_registers_pkg
\
work/gencores_pkg/.gencores_pkg
work/xloader_wb/.xloader_wb_vhd
:
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xloader_wb/.xloader_wb
:
\
work/wbgen2_pkg/.wbgen2_pkg
\
work/xloader_registers_pkg/.xloader_registers_pkg
work/spi_master/.spi_master_vhd
:
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/multiboot_fsm/.multiboot_fsm_vhd
:
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/multiboot_fsm/.multiboot_fsm
:
\
work/gencores_pkg/.gencores_pkg
work/multiboot_regs/.multiboot_regs_vhd
:
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_xil_multiboot/.xwb_xil_multiboot_vhd
:
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_xil_multiboot/.xwb_xil_multiboot
:
\
work/wishbone_pkg/.wishbone_pkg
sim/conv_man_trig/Manifest.py
0 → 100644
View file @
21f76124
target
=
"xilinx"
action
=
"simulation"
files
=
[
"testbench.vhd"
]
modules
=
{
"local"
:
"../../"
}
sim/conv_man_trig/run.do
0 → 100644
View file @
21f76124
vlib work
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
#add wave *
do wave.do
run 100 us
wave zoomfull
sim/conv_man_trig/testbench.vhd
0 → 100644
View file @
21f76124
--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for the manual trigger module
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-01-30
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-01-30 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
genram_pkg
.
all
;
use
work
.
conv_common_gw_pkg
.
all
;
entity
testbench
is
end
entity
testbench
;
architecture
behav
of
testbench
is
--============================================================================
-- Constant declarations
--============================================================================
constant
c_clk_per
:
time
:
=
50
ns
;
constant
c_reset_width
:
time
:
=
31
ns
;
--============================================================================
-- Functions and procedures
--============================================================================
procedure
f_mantrig
(
constant
chan
:
in
integer
;
signal
mpt
:
out
std_logic_vector
(
7
downto
0
);
signal
mpt_wr
:
out
std_logic
)
is
begin
wait
for
1
us
;
mpt
<=
x"de"
;
mpt_wr
<=
'1'
;
wait
for
c_clk_per
;
mpt_wr
<=
'0'
;
wait
for
1
us
;
mpt
<=
x"ad"
;
mpt_wr
<=
'1'
;
wait
for
c_clk_per
;
mpt_wr
<=
'0'
;
wait
for
1
us
;
mpt
<=
x"be"
;
mpt_wr
<=
'1'
;
wait
for
c_clk_per
;
mpt_wr
<=
'0'
;
wait
for
1
us
;
mpt
<=
x"ef"
;
mpt_wr
<=
'1'
;
wait
for
c_clk_per
;
mpt_wr
<=
'0'
;
wait
for
1
us
;
mpt
<=
std_logic_vector
(
to_unsigned
(
chan
,
8
));
mpt_wr
<=
'1'
;
wait
for
c_clk_per
;
mpt_wr
<=
'0'
;
wait
for
1
us
;
mpt_wr
<=
'1'
;
wait
for
c_clk_per
;
mpt_wr
<=
'0'
;
end
procedure
;
--============================================================================
-- Signal declarations
--============================================================================
signal
clk20
:
std_logic
:
=
'0'
;
signal
rst_n
:
std_logic
;
signal
mpt_wr
:
std_logic
;
signal
mpt_wr_d0
:
std_logic
;
signal
mpt_ld
:
std_logic
;
signal
mpt
:
std_logic_vector
(
7
downto
0
);
signal
trig_man
:
std_logic_vector
(
6
downto
1
);
signal
pulse
:
std_logic_vector
(
6
downto
1
);
signal
gf_n
:
std_logic
;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Generate clock and reset signals
--============================================================================
p_clk
:
process
begin
clk20
<=
not
clk20
;
wait
for
c_clk_per
/
2
;
end
process
p_clk
;
p_rst_n
:
process
begin
rst_n
<=
'0'
;
wait
for
c_reset_width
;
rst_n
<=
'1'
;
wait
;
end
process
p_rst_n
;
--============================================================================
-- Instantiate DUT and conv_pulse_gen blocks it drives
--============================================================================
-- First, the DUT
cmp_dut
:
conv_man_trig
generic
map
(
g_nr_chan
=>
6
,
g_pwidth
=>
10
)
port
map
(
clk_i
=>
clk20
,
rst_n_i
=>
rst_n
,
reg_ld_i
=>
mpt_ld
,
reg_i
=>
mpt
,
trig_o
=>
trig_man
);
-- Then, the pulse generators with a generate statement
gen_pulse_gens
:
for
i
in
1
to
6
generate
cmp_pulse_gen
:
conv_pulse_gen
generic
map
(
g_with_fixed_pwidth
=>
true
,
g_pwidth
=>
24
,
g_duty_cycle_div
=>
5
)
port
map
(
clk_i
=>
clk20
,
rst_n_i
=>
rst_n
,
gf_en_n_i
=>
gf_n
,
en_i
=>
'1'
,
trig_a_i
=>
trig_man
(
i
),
pulse_o
=>
pulse
(
i
)
);
end
generate
gen_pulse_gens
;
--============================================================================
-- Some stimuli for the DUT
--============================================================================
p_mpt_ld
:
process
(
clk20
)
begin
if
rising_edge
(
clk20
)
then
if
rst_n
=
'0'
then
mpt_ld
<=
'0'
;
mpt_wr_d0
<=
'0'
;
else
mpt_wr_d0
<=
mpt_wr
;
mpt_ld
<=
mpt_wr
and
not
mpt_wr_d0
;
end
if
;
end
if
;
end
process
;
p_stim
:
process
begin
mpt_wr
<=
'0'
;
mpt
<=
(
others
=>
'0'
);
--------------------------
-- No glitch filt
--------------------------
gf_n
<=
'1'
;
f_mantrig
(
6
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
6
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
5
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
5
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
4
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
4
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
3
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
3
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
2
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
2
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
1
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
1
,
mpt
,
mpt_wr
);
wait
for
1
us
;
--------------------------
-- With glitch filt
--------------------------
gf_n
<=
'0'
;
f_mantrig
(
6
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
6
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
5
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
5
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
4
,
mpt
,
mpt_wr
);
wait
for
1
us
;
gf_n
<=
'1'
;
f_mantrig
(
4
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
3
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
3
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
2
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
2
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
1
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
1
,
mpt
,
mpt_wr
);
wait
for
1
us
;
--------------------------
-- No glitch filt
--------------------------
gf_n
<=
'1'
;
f_mantrig
(
6
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
6
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
5
,
mpt
,
mpt_wr
);
wait
for
1
us
;
gf_n
<=
'0'
;
f_mantrig
(
5
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
4
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
4
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
3
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
3
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
2
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
2
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
1
,
mpt
,
mpt_wr
);
wait
for
1
us
;
f_mantrig
(
1
,
mpt
,
mpt_wr
);
wait
for
1
us
;
wait
;
end
process
p_stim
;
end
architecture
behav
;
--==============================================================================
-- architecture end
--==============================================================================
sim/conv_man_trig/wave.do
0 → 100644
View file @
21f76124
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk20
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/mpt_ld
add wave -noupdate /testbench/mpt
add wave -noupdate /testbench/trig_man
add wave -noupdate -expand /testbench/pulse
add wave -noupdate -divider DUT
add wave -noupdate /testbench/cmp_dut/state
add wave -noupdate /testbench/cmp_dut/pass
add wave -noupdate /testbench/cmp_dut/chnr
add wave -noupdate /testbench/cmp_dut/cnt
add wave -noupdate /testbench/cmp_dut/trig_o
add wave -noupdate -divider {glitch filt}
add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate -divider {pulse gen}
add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/pulse_gf_on
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {218986486 ps} 0} {{Cursor 2} {74966216 ps} 0}
configure wave -namecolwidth 383
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {315 us}
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