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conv-common-gw
Commit 052a9c2c authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Add FRONTFS and FRONTINVFS bits to LSR

parent d69919e6
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Showing with 60 additions and 22 deletions
modules/conv_regs.vhd
View file @ 052a9c2c
...@@ -168,6 +168,10 @@ entity conv_regs is ...@@ -168,6 +168,10 @@ entity conv_regs is
reg_lsr_frontinv_i : in std_logic_vector(3 downto 0); reg_lsr_frontinv_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR' -- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
reg_lsr_rear_i : in std_logic_vector(5 downto 0); reg_lsr_rear_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
reg_lsr_frontfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
reg_lsr_frontinvfs_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR' -- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
reg_lsr_rearfs_i : in std_logic_vector(5 downto 0); reg_lsr_rearfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR' -- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR'
...@@ -799,17 +803,9 @@ begin ...@@ -799,17 +803,9 @@ begin
rddata_reg(5 downto 0) <= reg_lsr_front_i; rddata_reg(5 downto 0) <= reg_lsr_front_i;
rddata_reg(9 downto 6) <= reg_lsr_frontinv_i; rddata_reg(9 downto 6) <= reg_lsr_frontinv_i;
rddata_reg(15 downto 10) <= reg_lsr_rear_i; rddata_reg(15 downto 10) <= reg_lsr_rear_i;
rddata_reg(21 downto 16) <= reg_lsr_rearfs_i; rddata_reg(21 downto 16) <= reg_lsr_frontfs_i;
rddata_reg(22) <= 'X'; rddata_reg(25 downto 22) <= reg_lsr_frontinvfs_i;
rddata_reg(23) <= 'X'; rddata_reg(31 downto 26) <= reg_lsr_rearfs_i;
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "100011" => when "100011" =>
......
modules/conv_regs.wb
View file @ 052a9c2c
...@@ -776,8 +776,32 @@ peripheral { ...@@ -776,8 +776,32 @@ peripheral {
access_bus = READ_ONLY; access_bus = READ_ONLY;
}; };
field { field {
name = "Input failsafe state"; name = "Front panel input failsafe state";
description = "High if line is in failsafe mode (no cable plugged in)\ description = "High if line is in failsafe mode (e.g., no cable plugged in)\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "frontfs";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Front panel inverter input failsafe state";
description = "High if line is in failsafe mode (e.g., no cable plugged in)\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "frontinvfs";
type = SLV;
size = 4;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Rear panel input failsafe state";
description = "High if line is in failsafe mode (e.g., no cable plugged in)\
Bit 0 -- channel 1\ Bit 0 -- channel 1\
Bit 1 -- channel 2\ Bit 1 -- channel 2\
etc."; etc.";
......
top/conv_common_gw.vhd
View file @ 052a9c2c
...@@ -178,6 +178,10 @@ entity conv_common_gw is ...@@ -178,6 +178,10 @@ entity conv_common_gw is
line_front_i : in std_logic_vector(g_nr_chans-1 downto 0); line_front_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_inv_i : in std_logic_vector(3 downto 0); line_inv_i : in std_logic_vector(3 downto 0);
line_rear_i : in std_logic_vector(g_nr_chans-1 downto 0); line_rear_i : in std_logic_vector(g_nr_chans-1 downto 0);
-- Fail-safe lines, detect invalid or no signal on channel input
line_front_fs_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_inv_fs_i : in std_logic_vector(3 downto 0);
line_rear_fs_i : in std_logic_vector(g_nr_chans-1 downto 0); line_rear_fs_i : in std_logic_vector(g_nr_chans-1 downto 0);
-- Thermometer line -- Thermometer line
...@@ -314,6 +318,7 @@ architecture arch of conv_common_gw is ...@@ -314,6 +318,7 @@ architecture arch of conv_common_gw is
signal i2c_err_bit_rst_ld : std_logic; signal i2c_err_bit_rst_ld : std_logic;
signal line_front : std_logic_vector(c_max_nr_chans-1 downto 0); signal line_front : std_logic_vector(c_max_nr_chans-1 downto 0);
signal line_rear : std_logic_vector(c_max_nr_chans-1 downto 0); signal line_rear : std_logic_vector(c_max_nr_chans-1 downto 0);
signal line_front_fs : std_logic_vector(c_max_nr_chans-1 downto 0);
signal line_rear_fs : std_logic_vector(c_max_nr_chans-1 downto 0); signal line_rear_fs : std_logic_vector(c_max_nr_chans-1 downto 0);
-- LED signals -- LED signals
...@@ -875,23 +880,26 @@ end generate gen_pulse_timetag; ...@@ -875,23 +880,26 @@ end generate gen_pulse_timetag;
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
gen_line : if (g_nr_chans = c_max_nr_chans) generate gen_line : if (g_nr_chans = c_max_nr_chans) generate
line_front <= line_front_i; line_front <= line_front_i;
line_rear <= line_rear_i; line_rear <= line_rear_i;
line_rear_fs <= line_rear_fs_i; line_front_fs <= line_front_fs_i;
line_rear_fs <= line_rear_fs_i;
end generate gen_line; end generate gen_line;
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
gen_line_unused_chans : if (g_nr_chans < c_max_nr_chans) generate gen_line_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
-- connect used lines -- connect used lines
line_front(g_nr_chans-1 downto 0) <= line_front_i; line_front(g_nr_chans-1 downto 0) <= line_front_i;
line_rear(g_nr_chans-1 downto 0) <= line_rear_i; line_rear(g_nr_chans-1 downto 0) <= line_rear_i;
line_rear_fs(g_nr_chans-1 downto 0) <= line_rear_fs_i; line_front_fs(g_nr_chans-1 downto 0) <= line_front_fs_i;
line_rear_fs(g_nr_chans-1 downto 0) <= line_rear_fs_i;
-- unused lines to zeroes -- unused lines to zeroes
line_front(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0'); line_front(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
line_rear(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0'); line_rear(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
line_rear_fs(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0'); line_front_fs(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
line_rear_fs(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
end generate gen_line_unused_chans; end generate gen_line_unused_chans;
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
...@@ -1168,6 +1176,8 @@ end generate gen_latest_timestamp_unused_chans; ...@@ -1168,6 +1176,8 @@ end generate gen_latest_timestamp_unused_chans;
reg_lsr_front_i => line_front, reg_lsr_front_i => line_front,
reg_lsr_frontinv_i => line_inv_i, reg_lsr_frontinv_i => line_inv_i,
reg_lsr_rear_i => line_rear, reg_lsr_rear_i => line_rear,
reg_lsr_frontfs_i => line_front_fs,
reg_lsr_frontinvfs_i => line_inv_fs_i,
reg_lsr_rearfs_i => line_rear_fs, reg_lsr_rearfs_i => line_rear_fs,
reg_oswr_switches_i => sw_other_i reg_oswr_switches_i => sw_other_i
......
top/conv_common_gw_pkg.vhd
View file @ 052a9c2c
...@@ -180,6 +180,10 @@ package conv_common_gw_pkg is ...@@ -180,6 +180,10 @@ package conv_common_gw_pkg is
line_front_i : in std_logic_vector(g_nr_chans-1 downto 0); line_front_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_inv_i : in std_logic_vector(3 downto 0); line_inv_i : in std_logic_vector(3 downto 0);
line_rear_i : in std_logic_vector(g_nr_chans-1 downto 0); line_rear_i : in std_logic_vector(g_nr_chans-1 downto 0);
-- Fail-safe lines, detect invalid or no signal on channel input
line_front_fs_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_inv_fs_i : in std_logic_vector(3 downto 0);
line_rear_fs_i : in std_logic_vector(g_nr_chans-1 downto 0); line_rear_fs_i : in std_logic_vector(g_nr_chans-1 downto 0);
-- Thermometer line -- Thermometer line
...@@ -419,6 +423,10 @@ package conv_common_gw_pkg is ...@@ -419,6 +423,10 @@ package conv_common_gw_pkg is
reg_lsr_frontinv_i : in std_logic_vector(3 downto 0); reg_lsr_frontinv_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR' -- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
reg_lsr_rear_i : in std_logic_vector(5 downto 0); reg_lsr_rear_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
reg_lsr_frontfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
reg_lsr_frontinvfs_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR' -- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
reg_lsr_rearfs_i : in std_logic_vector(5 downto 0); reg_lsr_rearfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR' -- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR'
......
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