• Theodor-Adrian Stana's avatar
    Added package file and made adjustments to output enable logic · 6e1a5f9e
    Theodor-Adrian Stana authored
    The main logic changes are that the output enable lines are now set after
    the internal reset has been spent. This is to make sure that the lines are
    only controlled by the FPGA and no erroneous glitches are generated.
    Other changes include the addition of the RTM detection lines to the
    interface, which are now reflected in the CONV Status Reg, and connecting
    the reset from register line, which was previously unconnected.
    Then, component instantiations and the SDB declaration for conv_regs have
    been moved to the package file (conv_common_gw_pkg).
Manifest.py 182 Bytes