Skip to content
GitLab
Explore
Sign in
Konstantinos Blantos
White Rabbit core collection
Repository
Branches
Overview
Active
Stale
All
tom-may13
db907e76
·
wr_gthe3_phy_family7: reset RX PCS after link loss to ensure reset of the bitslide counter
·
Jul 03, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
peter_spec7_v5_xwb_spi
4c737c3b
·
Add GPIO and SPI for LTC6950 to SPEC7 board file
·
Jul 06, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
tom-sis83k-aug25
8723297f
·
platform/xilinx: revert to Vivado-generated wrapper for GTHE3
·
Jul 17, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
tom-sis83k-jul17
8723297f
·
platform/xilinx: revert to Vivado-generated wrapper for GTHE3
·
Jul 17, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
wrs-lj-ext-ho-WRITE
95757b8c
·
Updated softpll regs for holdover board support
·
Jul 29, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
tom-afcz-aug25
d18df8d0
·
platform/xilinx: include Xilinx's GTHE4 IP in Manifest
·
Aug 06, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
tom-afcz-jul29
d18df8d0
·
platform/xilinx: include Xilinx's GTHE4 IP in Manifest
·
Aug 06, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
peter_spec7_v5_hpsec
9aa94408
·
test crap
·
Aug 07, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
tom-ertm14-aug25
bcf8ff2b
·
wr_core: expose UART FIFO configuration to wr_core generics
·
Aug 27, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
peter_spec7_v5_pll_sync
984a86f5
·
add dbg_o port
·
Aug 31, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
greg-pxie-fmc
62211821
·
pxie_fmc: add missing constraints file
·
Sep 07, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
nayib_spec7_txtsclk_fix
eac0e30a
·
Splitted the tx_timestamp signal in two clock domains; refclk for phys output, sysclk for lm32
·
Sep 09, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
peter_clbv2_3_4
f704f50e
·
Splitted the tx_timestamp signal in two clock domains; refclk for phys output, sysclk for lm32
·
Sep 11, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
tom-afcz-rebased
dae412fa
·
platform/xilinx: include Xilinx's GTHE4 IP in Manifest
·
Sep 11, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
tom-sis83k-rebased
4ff7c9a1
·
platform/xilinx: revert to Vivado-generated wrapper for GTHE3
·
Sep 11, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
pascal_spec7_v5
bf99cb6e
·
Added processing system to ref design.
·
Sep 14, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
guidov_spec7_v5_hpsec
fe9fac2f
·
Modified for the HPSEC the 125MHz input is own W5 and W6 125.000 MHz GTX reference
·
Sep 15, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
proposed_spec7
0c446e81
·
repaired pll_clk_sel_o being inverted
·
Sep 21, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
peter_spec7_v5
276cf6db
·
Repaired wrc_core memory map comment (due to Toms commit
3e433e26
"wrc_core:...
·
Sep 22, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
proposed_spec7_v5
276cf6db
·
Repaired wrc_core memory map comment (due to Toms commit
3e433e26
"wrc_core:...
·
Sep 22, 2020
Select Archive Format
Download source code
zip
tar.gz
tar.bz2
tar
Prev
1
2
3
4
5
6
7
8
Next