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White Rabbit core collection
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peter_201110
a0b3fb48
·
gen_10mhz avoid lut in reset path and add multicycle constraint due to tight 500 mhz timing.
·
Nov 10, 2020
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tom-nov06
d5952890
·
platform/xilinx/wr_gtp_phy: added Vivado-generated wrapper files for GTHE3
·
Nov 06, 2020
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tom-nov02
7771d098
·
wr_core: added generic to select LM32 RAM address space size (128/256 kB). Default = 128 kB
·
Nov 02, 2020
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peter_201007a
9ada6c39
·
gen_10mhz avoid lut in reset path and add multicycle constraint due to tight 500 mhz timing.
·
Oct 30, 2020
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gsi_master_get_back_on_track_oct2020_softpll_fix
7fc7954a
·
wr_core/softpll_ng: fixed irq bug
·
Oct 26, 2020
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tom-svec7
112099e2
·
wr_gtx_phy_family7: made clock buffers optional through generic
·
Oct 02, 2020
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peter_spec7_v5
276cf6db
·
Repaired wrc_core memory map comment (due to Toms commit
3e433e26
"wrc_core:...
·
Sep 22, 2020
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proposed_spec7_v5
276cf6db
·
Repaired wrc_core memory map comment (due to Toms commit
3e433e26
"wrc_core:...
·
Sep 22, 2020
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proposed_spec7
0c446e81
·
repaired pll_clk_sel_o being inverted
·
Sep 21, 2020
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guidov_spec7_v5_hpsec
fe9fac2f
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Modified for the HPSEC the 125MHz input is own W5 and W6 125.000 MHz GTX reference
·
Sep 15, 2020
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pascal_spec7_v5
bf99cb6e
·
Added processing system to ref design.
·
Sep 14, 2020
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tom-sis83k-rebased
4ff7c9a1
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platform/xilinx: revert to Vivado-generated wrapper for GTHE3
·
Sep 11, 2020
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tom-afcz-rebased
dae412fa
·
platform/xilinx: include Xilinx's GTHE4 IP in Manifest
·
Sep 11, 2020
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peter_clbv2_3_4
f704f50e
·
Splitted the tx_timestamp signal in two clock domains; refclk for phys output, sysclk for lm32
·
Sep 11, 2020
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nayib_spec7_txtsclk_fix
eac0e30a
·
Splitted the tx_timestamp signal in two clock domains; refclk for phys output, sysclk for lm32
·
Sep 09, 2020
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greg-pxie-fmc
62211821
·
pxie_fmc: add missing constraints file
·
Sep 07, 2020
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peter_spec7_v5_pll_sync
984a86f5
·
add dbg_o port
·
Aug 31, 2020
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tom-ertm14-aug25
bcf8ff2b
·
wr_core: expose UART FIFO configuration to wr_core generics
·
Aug 27, 2020
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peter_spec7_v5_hpsec
9aa94408
·
test crap
·
Aug 07, 2020
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tom-afcz-aug25
d18df8d0
·
platform/xilinx: include Xilinx's GTHE4 IP in Manifest
·
Aug 06, 2020
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