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hdl-core-lib
wr-cores
wrpc-sw
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740be374
Commit
740be374
authored
Oct 03, 2014
by
Benoit Rat
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wrs: disable 10MHz output (CLK1) until PLL is resync with WR.
parent
20cfb1c0
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ad9516.c
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dev/ad9516.c
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740be374
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@@ -260,6 +260,7 @@ int ad9516_init(int scb_version)
* Output 8 => 10 MHz
* Output 9 => 10 MHz
*/
ad9516_write_reg
(
0x143
,
0x1
);
//Temporary Powerdown 10MHz output
}
else
{
//Old one
...
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