Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
U
urv-core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
hdl-core-lib
urv-core
Commits
ecc50e05
Commit
ecc50e05
authored
Apr 21, 2018
by
Tomasz Wlostowski
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
sw: correctly emulate divide-by-zero case
parent
49cb85d2
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
5 additions
and
0 deletions
+5
-0
emulate.c
sw/common/emulate.c
+5
-0
No files found.
sw/common/emulate.c
View file @
ecc50e05
...
...
@@ -26,7 +26,12 @@ void undefined_insn_handler( struct rv_trap_context *ctx )
else
if
(
(
insn
&
0xfe00707f
)
==
0x2003033
)
// MULHU
ctx
->
r
[
rdi
]
=
((
uint64_t
)
rs1
*
(
uint64_t
)
rs2
)
>>
32
;
else
if
(
(
insn
&
0xfe00707f
)
==
0x2004033
)
// DIV
{
if
(
rs2
==
0
)
ctx
->
r
[
rdi
]
=
0xffffffff
;
else
ctx
->
r
[
rdi
]
=
(
int32_t
)
rs1
/
(
int32_t
)
rs2
;
}
else
if
(
(
insn
&
0xfe00707f
)
==
0x2005033
)
// DIVU
ctx
->
r
[
rdi
]
=
(
uint32_t
)
rs1
/
(
uint32_t
)
rs2
;
else
if
(
(
insn
&
0xfe00707f
)
==
0x2006033
)
// REM
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment