Remove dbg_insn_ready_o.

ddd3a4dc · Tristan Gingold · Dimitris Lampridis · 747a9dc1 · ddd3a4dc · ddd3a4dc
Commit ddd3a4dc authored Mar 14, 2018 by Tristan Gingold Committed by Dimitris Lampridis Mar 19, 2018
Hide whitespace changes
Inline Side-by-side

Showing with 32 additions and 29 deletions

urv_cpu.v rtl/urv_cpu.v +3 -6

urv_fetch.v rtl/urv_fetch.v +7 -13

main.sv tb/debug/main.sv +22 -10

No files found.
--- a/rtl/urv_cpu.v
+++ b/rtl/urv_cpu.v
@@ -60,14 +60,12 @@ module urv_cpu
   // is executed (from the dbg_insn_i port).
   // When debug mode is entered, dbg_enabled_o is set.  This may not be
   // immediate.  Interrupts are disabled in debug mode.
-   // In debug mode, instructions are executed from dbg_insn_i.  An instruction
-   // is fetched when dbg_insn_read_o is set.  As instructions are always
-   // fetched, they must be always valid.  Use a nop (0x13) if nothing should
-   // be executed.
+   // In debug mode, instructions are executed from dbg_insn_i.
+   // As instructions are always fetched, they must be always valid.  Use
+   // a nop (0x13) if nothing should be executed.
   input         dbg_force_i,
   output        dbg_enabled_o,
   input [31:0]  dbg_insn_i,
-   output        dbg_insn_ready_o,

   input [31:0]  dbg_mbxi_data_i,
   input         dbg_mbxi_write_i,
@@ -178,7 +176,6 @@ module urv_cpu
      .dbg_force_i(dbg_force_i),
      .dbg_enabled_o(dbg_enabled_o),
      .dbg_insn_i(dbg_insn_i),
-      .dbg_insn_ready_o(dbg_insn_ready_o),
      .x_dbg_toggle(x2f_dbg_toggle)
      );


--- a/rtl/urv_fetch.v
+++ b/rtl/urv_fetch.v
@@ -46,7 +46,6 @@ module urv_fetch
 input             dbg_force_i,
 output            dbg_enabled_o,
 input [31:0]      dbg_insn_i,
- output reg        dbg_insn_ready_o,
 input             x_dbg_toggle
 );

@@ -83,7 +82,6 @@ module urv_fetch

          //  Allow to start in debug mode.
          dbg_mode <= dbg_force_i;
-          dbg_insn_ready_o <= 0;

          pipeline_cnt <= 0;

@@ -108,7 +106,10 @@ module urv_fetch
                    //  Ebreak enters directly in the debug mode.  As it is
                    //  considered as a branch, stages are killed.
                    if (pipeline_cnt == 4 || x_dbg_toggle)
-                      dbg_mode <= 1;
+                      begin
+                         dbg_mode <= 1;
+                         pipeline_cnt <= 0;
+                      end
                    else
                      pipeline_cnt <= pipeline_cnt + 1;
                 end
@@ -119,22 +120,15 @@ module urv_fetch

                    if (x_dbg_toggle)
                      begin
-                         //  Leave debug mode
+                         //  Leave debug mode immediately.
                         dbg_mode <= 0;
-                         pipeline_cnt <= 0;
-                         // dbg_insn_ready_o must be 0.
+                         // pipeline_cnt must be 0.
                      end
-                    else if (dbg_insn_ready_o)
+                    else
                      begin
                         f_ir_o <= dbg_insn_i;
                         f_valid_o <= 1;
-                         dbg_insn_ready_o <= 0;
-                         pipeline_cnt <= 0;
                      end
-                    else if (pipeline_cnt == 4)
-                      dbg_insn_ready_o <= 1;
-                    else
-                      pipeline_cnt <= pipeline_cnt + 1;
                 end
               else if(im_valid_i)
                 begin

--- a/tb/debug/main.sv
+++ b/tb/debug/main.sv
@@ -47,7 +47,6 @@ module main;
   reg        dbg_force = 1;
   wire       dbg_enabled;
   reg [31:0] dbg_insn;
-   wire       dbg_insn_ready;

   reg [31:0] mbxi_data;
   reg        mbxi_write;
@@ -167,7 +166,6 @@ module main;
      .dbg_force_i(dbg_force),
      .dbg_enabled_o(dbg_enabled),
      .dbg_insn_i(dbg_insn),
-      .dbg_insn_ready_o(dbg_insn_ready),

      // Debug mailboxes
      .dbg_mbxi_data_i(mbxi_data),
@@ -183,9 +181,8 @@ module main;

   task send_insn (input [31:0] insn);
      dbg_insn <= insn;
-      while (!dbg_insn_ready)
-        @(posedge clk);
      @(posedge clk);
+      dbg_insn <= insn_nop;
   endtask // send_insn

   task send_mbxi(input [31:0] data);
@@ -203,16 +200,20 @@ module main;

      // write x1 to mbxo, jal x1, 0, write x1 to mbxo, read x1 from mbxi
      send_insn(insn_csrw_mbxo_ra);
+      send_insn(insn_mov_ra_pc4);
      send_insn(insn_nop);
+      send_insn(insn_nop);
+      //  Read ra only once the csrw has been executed.
      ra <= mbxo_data;
-      send_insn(insn_mov_ra_pc4);
      send_insn(insn_csrw_mbxo_ra);
-      send_insn(insn_nop);
-      pc <= mbxo_data - 4; // Jal save pc + 4
      mbxi_data <= ra;
      mbxi_write <= 1;
      send_insn(insn_csrr_ra_mbxi);
      mbxi_write <= 0;
+      send_insn(insn_nop);
+      send_insn(insn_nop);
+      pc <= mbxo_data - 4; // Jal save pc + 4
+      send_insn(insn_nop);

      $display("Break: pc=%x, ra=%x\n", pc, ra);
   endtask
@@ -241,11 +242,15 @@ module main;
           mbxi_data <= loader_addr + i * 4;
           mbxi_write <= 1;
           send_insn (insn_csrr_t0_mbxi);
+           send_insn (insn_nop);
+           send_insn (insn_nop);

           // Insn
           mbxi_data <= loader[i];
           mbxi_write <= 1;
           send_insn (insn_csrr_t1_mbxi);
+           send_insn (insn_nop);
+           send_insn (insn_nop);

           //  Store
           send_insn (insn_sw_t1_t0);
@@ -256,15 +261,18 @@ module main;
      mbxi_write <= 1;
      send_insn (insn_csrr_t0_mbxi);

-      //  Branch.
+      //  Branch and be sure it is executed.
      mbxi_write <= 0;
      send_insn (insn_jr_t0);
+      send_insn (insn_nop);
+      send_insn (insn_nop);

      //  Flush mailbox.
      send_insn (insn_csrr_t1_mbxi);

      send_insn (insn_ebreak);
-      dbg_insn <= insn_nop;
+      send_insn (insn_nop);
+      send_insn (insn_nop);

      //  Use loader to load the program.
      begin
@@ -300,6 +308,9 @@ module main;

      // Continue
      send_insn (insn_jmp_4);
+      send_insn (insn_nop);
+      send_insn (insn_nop);
+      send_insn (insn_nop);
      send_insn (insn_ebreak);
      dbg_insn <= insn_nop;

@@ -318,7 +329,8 @@ module main;

           // Continue
           send_insn (insn_ebreak);
-           dbg_insn <= insn_nop;
+           send_insn (insn_nop);
+           send_insn (insn_nop);
        end
   end