Minor clean-up.

c701e7ca · Tristan Gingold · 44d69a62 · c701e7ca · c701e7ca
Commit c701e7ca authored Mar 19, 2018 by Tristan Gingold
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urv_cpu.v rtl/urv_cpu.v +0 -1

urv_fetch.v rtl/urv_fetch.v +2 -3

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--- a/rtl/urv_cpu.v
+++ b/rtl/urv_cpu.v
@@ -95,7 +95,6 @@ module urv_cpu

   // F->D stage interface
   wire [31:0] 	 f2d_pc, f2d_ir;
-   wire 	 f2d_ir_valid;
   wire 	 f2d_valid;

   // D->RF interface

--- a/rtl/urv_fetch.v
+++ b/rtl/urv_fetch.v
@@ -115,17 +115,16 @@ module urv_fetch
                 end
               else if(dbg_mode)
                 begin
-                    //  Default: insn not valid
-                    f_valid_o <= 0;
-
                    if (x_dbg_toggle)
                      begin
                         //  Leave debug mode immediately.
                         dbg_mode <= 0;
+                         f_valid_o <= 0;
                         // pipeline_cnt must be 0.
                      end
                    else
                      begin
+                         //  Use instruction from the debug port.
                         f_ir_o <= dbg_insn_i;
                         f_valid_o <= 1;
                      end