Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
U
urv-core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
hdl-core-lib
urv-core
Commits
91e88f93
Commit
91e88f93
authored
Mar 19, 2018
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Run isa testsuite.
parent
2cf284ed
Hide whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
19 additions
and
22 deletions
+19
-22
riscv_test.h
sw/testsuite/env/p/riscv_test.h
+2
-2
test_macros.h
sw/testsuite/isa/macros/scalar/test_macros.h
+5
-5
main.sv
tb/cpu/main.sv
+7
-8
main.sv
tb/isa-testsuite/main.sv
+5
-7
No files found.
sw/testsuite/env/p/riscv_test.h
View file @
91e88f93
...
...
@@ -121,11 +121,11 @@ ecall: ecall; \
#define RVTEST_PASS \
la sp, _fstack; la gp, _gp; jal rv_test_pass; \
l
a t0, 0x100004; sw t0, 0
(t0); j ecall;
l
ui t0, %hi(0x100004); sw t0, %lo(0x100004)
(t0); j ecall;
#define RVTEST_FAIL \
la sp, _fstack; la gp, _gp; mv a0, TESTNUM; jal rv_test_fail;\
l
a t0, 0x100004; sw t0, 0
(t0); j ecall;
l
ui t0, %hi(0x100004); sw t0, %lo(0x100004)
(t0); j ecall;
//-----------------------------------------------------------------------
// Data Section Macro
...
...
sw/testsuite/isa/macros/scalar/test_macros.h
View file @
91e88f93
...
...
@@ -249,7 +249,7 @@ test_ ## testnum: \
#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
TEST_CASE( testnum, x3, result, \
l
a x1, base;
\
l
ui x1, %hi(base); addi x1, x1, %lo(base) ;
\
li x2, result; \
store_inst x2, offset(x1); \
load_inst x3, offset(x1); \
...
...
@@ -286,9 +286,9 @@ test_ ## testnum: \
test_ ## testnum: \
li TESTNUM, testnum; \
li x4, 0; \
1: l
a x1, result;
\
1: l
ui x1, %hi(result); addi x1, x1, %lo(result) ;
\
TEST_INSERT_NOPS_ ## src1_nops \
l
a x2, base;
\
l
ui x2, %hi(base); addi x2, x2, %lo(base) ;
\
TEST_INSERT_NOPS_ ## src2_nops \
store_inst x1, offset(x2); \
load_inst x3, offset(x2); \
...
...
@@ -302,9 +302,9 @@ test_ ## testnum: \
test_ ## testnum: \
li TESTNUM, testnum; \
li x4, 0; \
1: l
a x2, base;
\
1: l
ui x2, %hi(base); addi x2, x2, %lo(base) ;
\
TEST_INSERT_NOPS_ ## src1_nops \
l
a x1, result;
\
l
ui x1, %hi(result); addi x1, x1, %lo(result) ;
\
TEST_INSERT_NOPS_ ## src2_nops \
store_inst x1, offset(x2); \
load_inst x3, offset(x2); \
...
...
tb/cpu/main.sv
View file @
91e88f93
...
...
@@ -139,17 +139,16 @@ module main;
.
dm_ready_i
(
dm_ready
)
,
// Debug
.
dbg_force_i
(
0
)
,
.
dbg_force_i
(
1'b
0
)
,
.
dbg_enabled_o
()
,
.
dbg_insn_i
(
0
)
,
.
dbg_insn_i
(
32'h0
)
,
.
dbg_insn_set_i
(
1'b0
)
,
.
dbg_insn_ready_o
()
,
// Debug mailboxes
.
dbg_mbxi_data_i
(
32'h0
)
,
.
dbg_mbxi_valid_i
(
1'b0
)
,
.
dbg_mbxo_data_o
()
,
.
dbg_mbxo_valid_o
()
,
.
dbg_mbxo_read_i
(
1'b0
)
// Debug mailbox
.
dbg_mbx_data_i
(
0
)
,
.
dbg_mbx_write_i
(
1'b0
)
,
.
dbg_mbx_data_o
()
)
;
always
#
5
ns
clk
<=
~
clk
;
...
...
tb/isa-testsuite/main.sv
View file @
91e88f93
...
...
@@ -123,15 +123,13 @@ module main;
.
dbg_force_i
(
1'b0
)
,
.
dbg_enabled_o
()
,
.
dbg_insn_i
(
32'h0
)
,
.
dbg_insn_set_i
(
1'b0
)
,
.
dbg_insn_ready_o
()
,
// Debug mailboxes
.
dbg_mbxi_data_i
(
0
)
,
.
dbg_mbxi_write_i
(
1'b0
)
,
.
dbg_mbxi_full_o
()
,
.
dbg_mbxo_data_o
()
,
.
dbg_mbxo_full_o
()
,
.
dbg_mbxo_read_i
(
1'b0
)
// Debug mailbox
.
dbg_mbx_data_i
(
0
)
,
.
dbg_mbx_write_i
(
1'b0
)
,
.
dbg_mbx_data_o
()
)
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment