Add mt_ep_ethernet_single.

a06f916f · Tristan Gingold · c6caac2d · a06f916f · a06f916f
Commit a06f916f authored Jul 23, 2018 by Tristan Gingold
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Manifest.py hdl/rtl/endpoint/Manifest.py +1 -0

mt_ep_ethernet_single.vhd hdl/rtl/endpoint/mt_ep_ethernet_single.vhd +145 -0

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--- a/hdl/rtl/endpoint/Manifest.py
+++ b/hdl/rtl/endpoint/Manifest.py
@@ -11,5 +11,6 @@ files = [
    "mt_rmq_endpoint_tx.vhd",
    "mt_rmq_endpoint_rx.vhd",
    "mt_rmq_ethernet_endpoint.vhd",
+    "mt_ep_ethernet_single.vhd",
    "mt_endpoint_pkg.vhd"
 ];
--- a/hdl/rtl/endpoint/mt_ep_ethernet_single.vhd
+++ b/hdl/rtl/endpoint/mt_ep_ethernet_single.vhd
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- Mock Turtle
+-- https://gitlab.cern.ch/coht/mockturtle
+--------------------------------------------------------------------------------
+--
+-- unit name:   mt_ep_ethernet_single
+--
+-- description: Ethernet endpoint for a single Mock Turtle RMQ.
+--
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2014-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.mock_turtle_pkg.all;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.mt_mqueue_pkg.all;
+use work.gencores_pkg.all;
+use work.mt_endpoint_pkg.all;
+use work.wr_fabric_pkg.all;
+
+entity mt_ep_ethernet_single is
+  port (
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    --  Rx (eth -> RMQ)
+    rmq_src_i         : in  t_mt_stream_source_in;
+    rmq_src_o         : out t_mt_stream_source_out;
+    rmq_src_config_i  : in  t_mt_stream_config_out;
+    rmq_src_config_o  : out t_mt_stream_config_in;
+
+    --  TX (RMQ -> eth)
+    rmq_snk_i         : in  t_mt_stream_sink_in;
+    rmq_snk_o         : out t_mt_stream_sink_out;
+    rmq_snk_config_i  : in  t_mt_stream_config_out;
+    rmq_snk_config_o  : out t_mt_stream_config_in;
+
+    -- Fabric interface to the WR Core
+    eth_src_o : out t_wrf_source_out;
+    eth_src_i : in  t_wrf_source_in;
+    eth_snk_o : out t_wrf_sink_out;
+    eth_snk_i : in  t_wrf_sink_in
+    );
+end mt_ep_ethernet_single;
+
+architecture arch of mt_ep_ethernet_single is
+
+  signal config_out       : t_rmq_ep_tx_config;
+
+  signal wrsrc_snk_in, incoming_snk_in   : t_mt_stream_sink_in;
+  signal wrsrc_snk_out, incoming_snk_out : t_mt_stream_sink_out;
+  signal wrsnk_src_in                    : t_mt_stream_source_in;
+  signal wrsnk_src_out                   : t_mt_stream_source_out;
+  signal incoming_header_valid : std_logic;
+  signal incoming_header       : t_rmq_ep_rx_header;
+begin
+
+  --  TX
+
+  U_TX : entity work.mt_rmq_endpoint_tx
+    port map (
+      clk_i        => clk_i,
+      rst_n_i      => rst_n_i,
+      snk_config_i => rmq_snk_config_i,
+      snk_config_o => rmq_snk_config_o,
+      config_o     => config_out
+      );
+
+  U_TX_Path : entity work.mt_rmq_tx_path
+    port map (
+      clk_i    => clk_i,
+      rst_n_i  => rst_n_i,
+      snk_i    => rmq_snk_i,
+      snk_o    => rmq_snk_o,
+      src_i    => wrsrc_snk_out,
+      src_o    => wrsrc_snk_in,
+      config_i => config_out
+      );
+
+  U_WR_Source : entity work.mt_wr_source
+    port map (
+      clk_i   => clk_i,
+      rst_n_i => rst_n_i,
+      snk_i   => wrsrc_snk_in,
+      snk_o   => wrsrc_snk_out,
+      src_i   => eth_src_i,
+      src_o   => eth_src_o);
+
+  --  RX
+
+  U_RX : entity work.mt_rmq_endpoint_rx
+    port map (
+      clk_i          => clk_i,
+      rst_n_i        => rst_n_i,
+      header_valid_i => incoming_header_valid,
+      header_i       => incoming_header,
+      framer_snk_i   => incoming_snk_in,
+--      framer_snk_o   => incoming_snk_out,
+      mq_src_o       => rmq_src_o,
+      mq_src_i       => rmq_src_i,
+      snk_config_i   => rmq_src_config_i,
+      snk_config_o   => rmq_src_config_o);
+
+  U_RX_Path : entity work.mt_rmq_rx_path
+    port map (
+      clk_i            => clk_i,
+      rst_n_i          => rst_n_i,
+      snk_i            => wrsnk_src_out,
+      snk_o            => wrsnk_src_in,
+      src_i            => incoming_snk_out,
+      src_o            => incoming_snk_in,
+      p_header_valid_o => incoming_header_valid,
+      p_header_o       => incoming_header);
+
+  U_WR_Sink : entity work.mt_wr_sink
+    port map (
+      clk_i   => clk_i,
+      rst_n_i => rst_n_i,
+      snk_i   => eth_snk_i,
+      snk_o   => eth_snk_o,
+      src_o   => wrsnk_src_out,
+      src_i   => wrsnk_src_in);
+
+  incoming_snk_out.ready <= '1';
+
+
+end arch;