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Commit 590af67c authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Federico Vaga
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hdl/svec_mt_demo: invert master/slave on wb crossbar. 

Before, master/slave names were from the point of view of the wb crossbar ports. Slave for the VME core, Masters for the peripherals.

Now it is from the point of view of the devices. Master for the VME core, Slaves for the peripherals.
parent 6dba15b9
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Showing with 17 additions and 17 deletions
hdl/top/svec_mt_demo/svec_mt_demo.vhd
View file @ 590af67c
......@@ -102,8 +102,8 @@ architecture arch of svec_mt_demo is
others => (c_DUMMY_MT_MQUEUE_SLOT))))),
shared_mem_size => 2048);
constant c_NUM_WB_MASTERS : integer := 2;
constant c_NUM_WB_SLAVES : integer := 1;
constant c_NUM_WB_MASTERS : integer := 1;
constant c_NUM_WB_SLAVES : integer := 2;
constant c_MASTER_VME : integer := 0;
......@@ -112,7 +112,7 @@ architecture arch of svec_mt_demo is
constant c_DESC_SYNTHESIS : integer := 2;
constant c_DESC_REPO_URL : integer := 3;
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS + 1 downto 0) := (
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) := (
c_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB, x"00002000"),
c_SLAVE_MT => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000"),
c_DESC_SYNTHESIS => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO),
......@@ -275,8 +275,8 @@ begin -- architecture arch
vme_o.data_oe_n => VME_DATA_OE_N_b,
vme_o.addr_dir => VME_ADDR_DIR_int,
vme_o.addr_oe_n => VME_ADDR_OE_N_b,
wb_o => cnx_slave_in(c_MASTER_VME),
wb_i => cnx_slave_out(c_MASTER_VME),
wb_o => cnx_master_out(c_MASTER_VME),
wb_i => cnx_master_in(c_MASTER_VME),
int_i => vic_master_irq);
VME_DATA_b <= VME_DATA_b_out when VME_DATA_DIR_int = '1' else (others => 'Z');
......@@ -293,15 +293,15 @@ begin -- architecture arch
gen_without_vme64_core : if g_SIM_BYPASS_VME generate
-- synthesis translate_off
cnx_slave_in(c_MASTER_VME) <= sim_wb_i;
sim_wb_o <= cnx_slave_out(c_MASTER_VME);
cnx_master_out(c_MASTER_VME) <= sim_wb_i;
sim_wb_o <= cnx_master_in(c_MASTER_VME);
-- synthesis translate_on
end generate gen_without_vme64_core;
U_Intercon : xwb_sdb_crossbar
generic map (
g_NUM_MASTERS => c_NUM_WB_SLAVES,
g_NUM_SLAVES => c_NUM_WB_MASTERS,
g_NUM_MASTERS => c_NUM_WB_MASTERS,
g_NUM_SLAVES => c_NUM_WB_SLAVES,
g_REGISTERED => TRUE,
g_WRAPAROUND => TRUE,
g_LAYOUT => c_INTERCONNECT_LAYOUT,
......@@ -309,10 +309,10 @@ begin -- architecture arch
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
slave_i => cnx_master_out,
slave_o => cnx_master_in,
master_i => cnx_slave_out,
master_o => cnx_slave_in);
U_VIC : xwb_vic
generic map (
......@@ -323,8 +323,8 @@ begin -- architecture arch
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
slave_i => cnx_master_out(c_SLAVE_VIC),
slave_o => cnx_master_in(c_SLAVE_VIC),
slave_i => cnx_slave_in(c_SLAVE_VIC),
slave_o => cnx_slave_out(c_SLAVE_VIC),
irqs_i(0) => mt_hmq_in_irq,
irqs_i(1) => mt_hmq_out_irq,
irqs_i(2) => mt_console_irq,
......@@ -340,8 +340,8 @@ begin -- architecture arch
rst_n_i => rst_n_sys,
dp_master_o => dp_wb_out,
dp_master_i => dp_wb_in,
host_slave_i => cnx_master_out(c_SLAVE_MT),
host_slave_o => cnx_master_in(c_SLAVE_MT),
host_slave_i => cnx_slave_in(c_SLAVE_MT),
host_slave_o => cnx_slave_out(c_SLAVE_MT),
rmq_src_o => rmq_ds_o,
rmq_src_i => rmq_ds_i,
rmq_snk_o => rmq_us_o,
......
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