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hdl-core-lib
mock-turtle
Commits
54b56e39
Commit
54b56e39
authored
Feb 01, 2019
by
Dimitris Lampridis
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sim: disable verbose info messages from wishbone crossbars
parent
3f55ca7e
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4 changed files
with
5 additions
and
2 deletions
+5
-2
general-cores
hdl/ip_cores/general-cores
+1
-1
urv-core
hdl/ip_cores/urv-core
+1
-1
mt_cpu_cb.vhd
hdl/rtl/cpu/mt_cpu_cb.vhd
+1
-0
mock_turtle_core.vhd
hdl/rtl/mock_turtle_core.vhd
+2
-0
No files found.
general-cores
@
0ed0cf1d
Subproject commit
a50772ea3d4687226fbb6339bd951137946c7ad5
Subproject commit
0ed0cf1d2d8b21a9d92fea949a1ccaa03d9883a2
urv-core
@
5c7e906c
Subproject commit
70e9e78f740aa7f4d8168ccaa003bf3924824284
Subproject commit
5c7e906ceb6b15f53830061c9087cce0befef13a
hdl/rtl/cpu/mt_cpu_cb.vhd
View file @
54b56e39
...
...
@@ -385,6 +385,7 @@ begin -- arch
U_Local_Interconnect
:
xwb_crossbar
generic
map
(
g_VERBOSE
=>
FALSE
,
g_NUM_MASTERS
=>
1
,
g_NUM_SLAVES
=>
c_SLAVE_NUM
,
g_REGISTERED
=>
TRUE
,
...
...
hdl/rtl/mock_turtle_core.vhd
View file @
54b56e39
...
...
@@ -275,6 +275,7 @@ begin -- arch
U_Host_Access_CB
:
xwb_crossbar
generic
map
(
g_VERBOSE
=>
FALSE
,
g_NUM_MASTERS
=>
1
,
g_NUM_SLAVES
=>
c_HAC_WISHBONE_MASTERS
,
g_REGISTERED
=>
TRUE
,
...
...
@@ -291,6 +292,7 @@ begin -- arch
U_Shared_Interconnect
:
xwb_crossbar
generic
map
(
g_VERBOSE
=>
FALSE
,
g_NUM_MASTERS
=>
c_SI_WISHBONE_SLAVES
,
g_NUM_SLAVES
=>
c_SI_WISHBONE_MASTERS
,
g_REGISTERED
=>
TRUE
,
...
...
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