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hdl-core-lib
mock-turtle
Commits
4a0e7301
Commit
4a0e7301
authored
Jul 25, 2018
by
Dimitris Lampridis
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hdl: fix building of svec_mt_demo_wr
parent
80e0f4c8
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.gitignore
hdl/syn/svec_mt_demo_wr/.gitignore
+4
-0
svec_mt_demo_wr.xise
hdl/syn/svec_mt_demo_wr/svec_mt_demo_wr.xise
+0
-1314
svec_mt_demo_wr.vhd
hdl/top/svec_mt_demo_wr/svec_mt_demo_wr.vhd
+1
-1
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hdl/syn/svec_mt_demo_wr/.gitignore
0 → 100644
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4a0e7301
*
!.gitignore
!Manifest.py
!svec_mt_demo_wr.ucf
hdl/syn/svec_mt_demo_wr/svec_mt_demo_wr.xise
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hdl/top/svec_mt_demo_wr/svec_mt_demo_wr.vhd
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4a0e7301
...
...
@@ -510,7 +510,7 @@ begin -- architecture arch
generic
map
(
g_simulation
=>
f_to_integer
(
g_simulation
),
g_with_external_clock_input
=>
false
,
g_dpram_initf
=>
"
wrc
.bram"
,
g_dpram_initf
=>
"
../../ip_cores/wr-cores/bin/wrpc/wrc_phy8
.bram"
,
g_fabric_iface
=>
PLAIN
)
port
map
(
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
...
...
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