Fix bug in whisbone interface, was not working with single wb cycle rd/wr…

Fix bug in whisbone interface, was not working with single wb cycle rd/wr because the cmd_instr was taken from wb_we instead of wb_we_d. git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@83 739e5516-d4a2-47df-ba96-5610c1fa693f

Fix bug in whisbone interface, was not working with single wb cycle rd/wr…
Fix bug in whisbone interface, was not working with single wb cycle rd/wr because the cmd_instr was taken from wb_we instead of wb_we_d. git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@83 739e5516-d4a2-47df-ba96-5610c1fa693f
e86407ee · mcattin · 4dddc439 · e86407ee
Commit e86407ee authored Dec 06, 2011 by mcattin
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ddr3_ctrl_wb.vhd hdl/rtl/ddr3_ctrl_wb.vhd +1 -1

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--- a/hdl/rtl/ddr3_ctrl_wb.vhd
+++ b/hdl/rtl/ddr3_ctrl_wb.vhd
@@ -229,7 +229,7 @@ begin
        if ((ddr_burst_cnt = 0 and wb_cyc_r_edge = '1' and wb_stb_i = '1') or
            (ddr_burst_cnt = to_unsigned(1, ddr_burst_cnt'length))) then
          ddr_cmd_byte_addr <= wb_addr_d(g_BYTE_ADDR_WIDTH-c_ADDR_SHIFT-1 downto 0) & addr_shift;
-          ddr_cmd_instr     <= "00" & not(wb_we_i);
+          ddr_cmd_instr     <= "00" & not(wb_we_d);
        end if;
        ddr_cmd_bl <= std_logic_vector(ddr_burst_cnt - 1);
      end if;