layout-v3.1
All issues for this milestone are closed. You may close the milestone now.
Project | Open issues | State | Due date |
---|---|---|---|
fmc-nanofip | 0 | Open |
Unstarted Issues (open and unassigned)
0
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
13
- fmc-nanofip · R78 and J2 seem to overlap
- fmc-nanofip · Using the DRB TPS7A49 variant (VSON package) might lead to better reliability
- fmc-nanofip · FMC VREF_A_M2C should be not connected
- fmc-nanofip · Bottom: power tracks could be wider (currently they are 0.2mm)
- fmc-nanofip · TPS7A49 (IC2, IC3, IC6) layout could be improved
- fmc-nanofip · L3: unconnected stub of VBUS polygon between two tracks
- fmc-nanofip · change silkscreen license text to CERN OHL-W v2
- fmc-nanofip · add more stitching vias to connect well different GND planes
- fmc-nanofip · L6: P1V5 polygon is spread over the whole PCB area with very few connections (vias)
- fmc-nanofip · missing _N suffix for JC_TRST (instead of over-line)
- fmc-nanofip · Test points: change to through hole and add labels
- fmc-nanofip · '5M' label is slightly off
- fmc-nanofip · Test points: TP1,2,3,4 very close to the front panel; cannot be probed