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Consider adding pin swapping groups to the FPGA
diot-pfc-ku#64
· opened
Nov 26, 2020
by
Christos Gentsos
layout-v1.0
Done
minor
CLOSED
3
updated
Sep 06, 2021
Remove wires from unused FPGA pins
diot-pfc-ku#62
· opened
Nov 23, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
1
updated
Sep 06, 2021
different thickness of DDR lines depending on layer?
diot-pfc-ku#84
· opened
Jul 20, 2021
by
Grzegorz Daniluk
layout-v1.0
question
CLOSED
2
updated
Jul 21, 2021
Missing table with layers stackup and total board thickness
diot-pfc-ku#81
· opened
Jul 20, 2021
by
Grzegorz Daniluk
layout-v1.0
minor
CLOSED
2
updated
Jul 21, 2021
polygons on signal layer
diot-sb-zu#198
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Major
CLOSED
8
updated
Jul 21, 2021
[L1, L14] IC30, IC31 - add more vias on the thermal pads and expose (no soldermask) GND area on bottom layer.
diot-sb-zu#155
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Jul 20, 2021
[FPGA_Bank_66_67_68_DDR] forbidden I/O assignment
diot-pfc-ku#76
· opened
Jul 06, 2021
by
Grzegorz Daniluk
layout-v1.0
major
CLOSED
1
updated
Jul 07, 2021
The P1V5 and VADJ planes stray unneccessarily
fmc-profinet#90
· opened
Jun 03, 2021
by
Christos Gentsos
layout-v1.0
Layout Review V1.0
CLOSED
4
updated
Jun 08, 2021
Consider making core between L6 and L7 thicker
fmc-profinet#91
· opened
Jun 03, 2021
by
Christos Gentsos
layout-v1.0
Layout Review V1.0
CLOSED
1
updated
Jun 07, 2021
DC/DC layout issues
fmc-profinet#60
· opened
Mar 17, 2021
by
Christos Gentsos
layout-v1.0
critical
Layout Review V1.0
CLOSED
3
updated
Jun 03, 2021
L10: expand Vadj plane at X:4962mil Y:4289mil
fmc-profinet#87
· opened
May 06, 2021
by
Grzegorz Daniluk
layout-v1.0
CLOSED
1
updated
Jun 03, 2021
Remove GND polygons from signal layers
fmc-profinet#68
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
1
updated
Jun 03, 2021
The ERTEC IC is missing decoupling capacitors on its Vadj bank
fmc-profinet#88
· opened
May 07, 2021
by
Christos Gentsos
layout-v1.0
Layout Review V1.0
CLOSED
2
updated
Jun 03, 2021
The P1V5 plane gets way too thin at certain points
fmc-profinet#89
· opened
May 10, 2021
by
Christos Gentsos
layout-v1.0
Layout Review V1.0
CLOSED
2
updated
Jun 03, 2021
[L1] X:4800mil, Y:4100mil mix of tracks and GND polygon create acid traps
fmc-profinet#55
· opened
Mar 16, 2021
by
Grzegorz Daniluk
layout-v1.0
CLOSED
1
updated
May 17, 2021
[L10] X:5200mil Y:3900mil P3V3A polygon stretch can be removed as it does not connect to anything
fmc-profinet#76
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
cosmetics
CLOSED
1
updated
May 17, 2021
Routing for memories
fmc-profinet#77
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
question
CLOSED
2
updated
May 17, 2021
[L1] X:4653mil Y:4085mil very thin 4mil track to P3V3 decoupling cap
fmc-profinet#75
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
CLOSED
1
updated
May 17, 2021
FMC connector: Use separate via for each power pin
fmc-profinet#71
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
1
updated
May 17, 2021
Memories should be routed in a fly-by topology
fmc-profinet#61
· opened
Mar 17, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
2
updated
May 17, 2021
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