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Crosstalk
svec7#97
· opened
Jul 08, 2020
by
Evangelia Gousiou
Ready for V1 prototype
minor
CLOSED
4
updated
Jul 19, 2020
Diff pairs impedance
svec7#96
· opened
Jul 08, 2020
by
Evangelia Gousiou
Ready for V1 prototype
design
major
CLOSED
3
updated
Aug 13, 2020
PCB version
svec7#94
· opened
Jul 08, 2020
by
Evangelia Gousiou
Ready for V1 prototype
design
major
CLOSED
3
updated
Jul 19, 2020
Project name
svec7#93
· opened
Jul 08, 2020
by
Evangelia Gousiou
Ready for V1 prototype
minor
CLOSED
3
updated
Jul 22, 2020
FMC DP should be length matched
svec7#90
· opened
Jul 06, 2020
by
Grzegorz Daniluk
Ready for V1 prototype
design
minor
CLOSED
4
updated
Aug 20, 2020
FMC LA should be length matched
svec7#89
· opened
Jul 06, 2020
by
Grzegorz Daniluk
Ready for V1 prototype
design
major
CLOSED
3
updated
Jul 22, 2020
update copyright in schematics and license to CERN OHL v2
svec7#87
· opened
Jul 06, 2020
by
Grzegorz Daniluk
Ready for V1 prototype
minor
CLOSED
1
updated
Aug 13, 2020
No heatsink on K7
svec7#69
· opened
Jun 01, 2020
by
Paweł Kulik
Ready for V1 prototype
CLOSED
2
updated
Jul 22, 2020
AFPGA can't be programmed from SFPGA on-the-fly
svec7#58
· opened
Apr 20, 2020
by
Tomasz Wlostowski
Ready for V1 prototype
critical
CLOSED
1
updated
Jul 22, 2020