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Front-panel design and fabrication
wr2rf-vme#79
· opened
Jan 29, 2021
by
Erik van der Bij
Layout V2
for-DEM
important
CLOSED
1
updated
Jul 06, 2021
The PCB labelling of the SFP connectors is inconsistent with front panel labelling
wr2rf-vme#76
· opened
Jan 22, 2021
by
John Gill
Layout V2
for-DEM
CLOSED
1
updated
Feb 15, 2021
Front panel cannot be fitted
wr2rf-vme#80
· opened
Jan 29, 2021
by
John Gill
Layout V2
for-DEM
important
CLOSED
2
updated
Feb 15, 2021
Front panel: J9 very close to the front panel handle
wr2rf-vme#83
· opened
Feb 05, 2021
by
Tomasz Wlostowski
Layout V2
for-DEM
CLOSED
1
updated
Feb 15, 2021
Change electrolytic caps to more reliable series
wr2rf-vme#84
· opened
Feb 05, 2021
by
Tomasz Wlostowski
Layout V2
for-DEM
CLOSED
1
updated
Feb 15, 2021
Cross check PCB labelling with front panel for the SFP indexing
wr2rf-vme#68
· opened
Dec 14, 2020
by
John Gill
Layout V2
cosmetics
for-DEM
hdl
hw
CLOSED
2
updated
Feb 15, 2021
V2: change EP195 delay line to SY89295UMG
wr2rf-vme#86
· opened
Feb 11, 2021
by
Tomasz Wlostowski
Layout V2
for-DEM
CLOSED
2
updated
Feb 15, 2021
Front panel middle fastening not aligned with PCB
wr2rf-vme#81
· opened
Jan 29, 2021
by
John Gill
Layout V2
for-DEM
CLOSED
4
updated
Feb 12, 2021
EXT REF I/O: PPS / 10M mux direction line needs opposite polarity
wr2rf-vme#85
· opened
Feb 05, 2021
by
Tomasz Wlostowski
Layout V2
minor
CLOSED
1
updated
Feb 05, 2021
RF signal, distributed to trigger unit flip flops looks awful
wr2rf-vme#74
· opened
Jan 22, 2021
by
John Gill
Layout V2
critical
hw
CLOSED
2
updated
Feb 05, 2021
Unconnected 5V power rail
wr2rf-vme#69
· opened
Dec 14, 2020
by
John Gill
Layout V2
critical
hw
CLOSED
1
updated
Feb 05, 2021
Change license to CERN-OHL-W
wr2rf-vme#67
· opened
Oct 23, 2020
by
Tomasz Wlostowski
Layout V2
for-DEM
CLOSED
0
updated
Feb 05, 2021
SFP LEDs are on when FPGA is not programmed
wr2rf-vme#70
· opened
Dec 14, 2020
by
Dimitris Lampridis
Layout V2
hw
minor
CLOSED
2
updated
Feb 05, 2021
WRC eeprom are too small
wr2rf-vme#72
· opened
Dec 14, 2020
by
Tristan Gingold
Layout V2
hw
CLOSED
1
updated
Feb 05, 2021
OCXO sense goes to FPGA digital input
wr2rf-vme#71
· opened
Dec 14, 2020
by
Dimitris Lampridis
Layout V2
hw
important
CLOSED
1
updated
Feb 05, 2021