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- changed SPEC synthesis to ISE (was Synplify)
- general cleanup

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spec: removed dma; timestamps to be retrieved through wishbone (not stable yet; code needs bit of cleaning!)

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different wishbone interface on fmc_tdc_mezzanine for timestamps retrieval (goes to dma for spec and to crossbar for svec) 

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small changes on vic addressing

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- changed IOBs settings (map -pr) on svec tdc; now no extra cycle needed in the acam_databus_interface.vhd for the ef, rd_n communication with the acam.
- added comments and architecture drawings on top of the modules 

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