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  • PHASE (Portable Hardware Analyzer with Sharing Explorer) aims at unifying hardware debugging in a single tool. From the host machine, a user may graphically interconnect components to describe the connection between his computer and the target device to debug. For example, a USB JTAG cable might be the root node, connected to an Arria2 development board with a CPLD and an FPGA, containing a LM32 processor.

    Wherever possible, PHASE fetches design descriptions from the internet based on the detected JTAG IDCODEs, USB vendor IDs, or PnP BUS information. In the preceding example, each step of the chain would be automatically detected. The USB cable from the vendor+product codes, the FPGA from the JTAG IDCODE and the LM32 from the Arria2's sld hub. The user would now be presented with read/write access to the data and instruction buses for visual inspection or firmware loading. Furthermore, the user could launch gdb to halt and single-step the embedded LM32 CPU.

    If a device is not yet described, the user may assemble a driver out of the reusable software components. For example, an Altera USB-Blaster driver is just a FTDI device chained with a byte packeter and a JTAG bit banger. Once the design has been graphically assembled, it is automatically scanned for attached JTAG devices and the USB cable design is shared online with any future users of the same cable.

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  • The robustness of a White Rabbit Network (WRN) is a broad subject covering methods (HW & SW) which enable to increase overall reliability of a WR-based system. This includes Forward Error Correction (FEC), Quality of Service (QoS) assurance, support of network redundancy, proper network design, thorough diagnostics, and increasing the reliability of network components (i.e. switches, nodes). Here, these methods are described and their implementation sources gathered.

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  • Software for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.

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  • This is a port of an older Linux ptpd to support White Rabbit extensions and run both in hosted and freestanding environment. In the future we plan to replace it with PPSI, which has a much better design, but ptp-noposix is currently working pretty well despite being difficult to maintain.

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  • MMC firmware written in C, running on a microcontroller inside the board. Written first for the AFC boards. This firmware is thought to be generic enough so other AMC boards could reuse a large part of it. For now, the only "port" is for the LPC1764 chip, but more are planned.

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  • A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor. Software.

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  • This is a collection of simple macro implementations for Microsemi's ProASIC3 FPGAs to allow simulating post-synthesis designs using GHDL.

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  • This library provides a generic API for ADC devices, so that applications can use this API to access any of the supported ADC boards. Currently the library supports the following boards:

    fmc-adc-100m14b14cha

    For testing and debugging purpose it supports also a couple of virtual boards that you can use to start the development of your application.

    More info at the Wiki page

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  • The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page

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  • A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.

    The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.

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  • Software to support the fmc-adc-100m14b4cha mezzanine, including Linux device driver, library and test program.

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  • A VHDL core for a PCI slave. The other side behaves like a Wishbone master.

    More info at the Wiki page
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  • Configuration and boot software required to start up the SPEC7 board

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  • Test. May be deleted.

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  • Powerlink Industrial Ethernet stack. It runs on top of the Hydra rad-tol SoC project. More info at the Wiki page

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  • Tester board to test PXIe processor modules. Two variants: slot 2 and slot 10 (system timing slot). More info at the Wiki page

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  • This library provides a generic API for ADC devices, so that applications can use this API to access any of the supported ADC boards. Currently the library supports the following boards:

    fmc-adc-100m14b14cha

    For testing and debugging purpose it supports also a couple of virtual boards that you can use to start the development of your application.

    More info at the Wiki page

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