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Production and functional tests for PXIe controller COM Express based. More info at the Wiki page

This project contains gateware for the Distributed IO Tier demonstrator according to the CERN Warm Interlocks specification

High-resolution frequency/phase-microstepper for timing laboratories. More info at the Wiki page

The open-source HEV ventilator implements the modes PC-A/C, PC-A/C-PRVC, PC-PSV and CPAP More info at the Wiki page

Tester board to test PXIe processor modules. Two variants: slot 2 and slot 10 (system timing slot). More info at the Wiki page

Test. May be deleted.

Configuration and boot software required to start up the SPEC7 board

A VHDL core for a PCI slave. The other side behaves like a Wishbone master.

More info at the Wiki page

Open Breath lung ventilator. It is developed to be low-cost, scalable and easily manufactured. It can be used in Pressure and Volume Control, SIMV+PS and CPAP functions. More info at the Wiki page

MMC firmware written in C, running on a microcontroller inside the board. Written first for the AFC boards. This firmware is thought to be generic enough so other AMC boards could reuse a large part of it. For now, the only "port" is for the LPC1764 chip, but more are planned.

This is a port of an older Linux ptpd to support White Rabbit extensions and run both in hosted and freestanding environment. In the future we plan to replace it with PPSI, which has a much better design, but ptp-noposix is currently working pretty well despite being difficult to maintain.

Software for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.

The robustness of a White Rabbit Network (WRN) is a broad subject covering methods (HW & SW) which enable to increase overall reliability of a WR-based system. This includes Forward Error Correction (FEC), Quality of Service (QoS) assurance, support of network redundancy, proper network design, thorough diagnostics, and increasing the reliability of network components (i.e. switches, nodes). Here, these methods are described and their implementation sources gathered.

PHASE (Portable Hardware Analyzer with Sharing Explorer) aims at unifying hardware debugging in a single tool. From the host machine, a user may graphically interconnect components to describe the connection between his computer and the target device to debug. For example, a USB JTAG cable might be the root node, connected to an Arria2 development board with a CPLD and an FPGA, containing a LM32 processor.

Wherever possible, PHASE fetches design descriptions from the internet based on the detected JTAG IDCODEs, USB vendor IDs, or PnP BUS information. In the preceding example, each step of the chain would be automatically detected. The USB cable from the vendor+product codes, the FPGA from the JTAG IDCODE and the LM32 from the Arria2's sld hub. The user would now be presented with read/write access to the data and instruction buses for visual inspection or firmware loading. Furthermore, the user could launch gdb to halt and single-step the embedded LM32 CPU.

If a device is not yet described, the user may assemble a driver out of the reusable software components. For example, an Altera USB-Blaster driver is just a FTDI device chained with a byte packeter and a JTAG bit banger. Once the design has been graphically assembled, it is automatically scanned for attached JTAG devices and the USB cable design is shared online with any future users of the same cable.