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Mathieu Saccani / VME64x core - msaccani
GNU Lesser General Public License v2.1 onlyA VHDL core for a VME64x slave. The other side behaves like a Wishbone master.
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This project contains gateware for the Distributed IO Tier demonstrator according to the CERN Warm Interlocks specification
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A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.
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A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).
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This project contains all the HDL gateware necessary for the FPGA of the WR switch.
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The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA
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