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Programmable attenuator of RF signals with very high voltage range (50mV – 1000 V) for protecting digitizers against damage by high voltage signals. Four channels with SMA connectors; Three attenuation values: 0, -20, -40 dB; Bandwidth: DC – 2 GHz.

Configuration and boot software required to start up the SPEC7 board

Open design and implementation of a low-cost ventilator for COVID-19 patients. More info at the Wiki page

A simple 4-lane PCIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. Commercially available. Linux and Labview drivers available for some mezzanine cards. More info at the Wiki page

An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page

A simple VME64x carrier for two low pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Commercially available. More info at the Wiki page

A cute-wr is a compact WR-node implementation with minimum components required. The initial design is derived from SPEC, but would work in an opposite manner as a FMC wr-nic, providing 2 DIO channels, external CLK input, EEPROM, JTAG, RS232, and expandable IOs through FMC connector. The gateware and software of cute-wr would also keep maximum compatibility with SPEC. Project is obsolete. See cute-wr-dp for a similar board.

Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page

A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor. Testing.

Compact Universal Timing Endpoint Based on White Rabbit with Xilinx Artix7. Follow-up of the CUTE-WR-DP. More info at the Wiki page

FMC LPC card with two High Voltage (HV) outputs and one Low Voltage (5-10V) output. Has mV voltage sensing and mA current sensing capabilities. More info at the Wiki page

Collection of WRTD reference designs provided by (and used at) CERN

Idrogen is an Arria10 FPGA board with FMC mezzanine.

PCB design is performed by IJCLab / CNRS-IN2P3. Firmware is developed by Observatoire Radioastronomique de Nançay (ORN) / Observatoire de Paris/ CNRS-INSU

Host-side software support for the TDC FMC on the SPEC and SVEC FMC carriers.

More info at the Wiki page

HW project: https://www.ohwr.org/project/fmc-tdc/wiki

ADC testing procedures and software. More info at the Wiki page

A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.

More info at the Wiki page

A software suite written in Python to help with production tests of PCBs. AKA PTS.

%(red)This pts-base project is used to re-organise the current pts project In the future this project will replace the existing pts project.

More info at the Wiki page

Legacy-VME64x core implements a legacy VME (VMEbus IEEE-1014) and VME64x (based on the vme64x-core) slave.

The core offers for SoC interconnection:

Master WB interconnection and Slave WB for MSI IRQ.

The core also provides a universal layer abstraction for common hardware components in VME design (e.g VME buffers). It allows for geographical and hardware switch addressing. More info at the Wiki page

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page