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Projects / LHC Instability Trigger Distribution LIST
GNU General Public License v3.0 onlyLIST is a trigger distribution system based on White Rabbit. It can receive a trigger from a “cloud” of devices and distribute it to all relevant devices to for example freeze their acquisition buffers. The latency between reception and transmission of a trigger is done with a low and notably fixed latency, with an accuracy of better than 1 ns. The hardware of the LIST nodes is based on the SVEC FMC carrier equipped with a FMC TDC mezzanine and a Fine Delay mezzanine. More info at the Wiki page
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LIBSFP is a software library that contains generic functions to access SFP devices via I2C.
More info can be found on this wiki page.
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The GSI Timing Starter Kit is a functional snapshot of the eventual FAIR timing system, which is under active development. It demonstrates real-time coordination of two front-end equipment controllers. The product consists of a data master (Linux PC) which coordinates events, a timing master which synchronizes clocks (White Rabbit switch), and two front-end equipment controllers (either SPECv4 or SCUv2).
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This project defines data structures, to be embedded in the FPGA memory address space, to enumerate the devices that have been synthetized in the current design. The same structure is also used as a simple flash file system. AKA Self-Describing Bus (SDB) Specification for Logic Cores. The layout is simple enough to be parsed both by the host and by the internal soft-core, if any.
The documentation is public, and related code is GNU GPL licensed.
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Projects / FMC TDC 1ns 5cha - Software
GNU General Public License v2.0 or laterHost-side software support for the TDC FMC on the SPEC and SVEC FMC carriers.
HW project: https://www.ohwr.org/project/fmc-tdc/wikiUpdated -
Production and functional tests for FMC TDC 1ns 5cha.
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Gateware (HDL design) for FMC TDC 1ns 5cha on SPEC and SVEC carriers.
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FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os on LEMO 00 connectors are TTL compatible. Commercially available. More info at the Wiki page
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Projects / FMC DEL 1ns 4cha - stand-alone application
GNU General Public License v3.0 onlyA fully operational stand-alone FMC Delay card based White-Rabbit node which can be initialized and perform periodic calibrations without requiring to be plugged on a PC, reducing final system cost, size and power consumption. More info at the Wiki page
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Projects / FMC Bus
GNU General Public License v2.0 or laterThe FMC bus abstraction implements a Linux kernel bus named fmc. This allows to deal with FMC mezzanines in a carrier-independent way
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Gateware (HDL design) for FMC ADC 400k 18b 4cha iso on SPEC and SVEC carriers.
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EPICS support for Wishbone peripherals: This project consist of a Generic EPICS IOC AsynDriver to support wishbone peripheral. It include the following features:
Driver for X1052, Gennum, Etherbone WB master. Direct access to any register in the wishbone bus Auto-generation of EPICS Database file using wbgen2 Automatic real number convertion (2 complements, fixed point, signess) using .wb file Support for WR Core and other internal bus protocols (i2c, spi, etc.)Updated -
Projects / DCES-DTRHF-SER1CH-v1
GNU General Public License v3.0 onlyData centre environmental sensor - Dust, Temperature, Relative Humidity, Fan - Serial 1 channel - version 1. An environmental sensor for Data Centers that continuously measures airborne particle density in high airflow as well as temperature and relative humidity. It can control its fan speed if needed (PWM controlled fans) and monitors FAN rotational speed (tachometer equipped fans) for precise airflow control and monitoring. It is close to maintenance free and can be integrated in compact enclosures (for example tape drive tray or even an ATX PSU case...). More info at the Wiki page
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A cute-wr is a compact WR-node implementation with minimum components required. The initial design is derived from SPEC, but would work in an opposite manner as a FMC wr-nic, providing 2 DIO channels, external CLK input, EEPROM, JTAG, RS232, and expandable IOs through FMC connector. The gateware and software of cute-wr would also keep maximum compatibility with SPEC. Project is obsolete. See cute-wr-dp for a similar board.
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Production and functional tests for Conv TTL Blocking. More info at the Wiki page
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Gateware (VHDL) for the level conversion board Conv TTL Blocking in VME64x form factor between TTL and blocking levels. More info at the Wiki page
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Common gateware for the different level conversion circuits.
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A system to characterize large area silicon pad sensors with several hundred channels. This repository contains the microcontroller firmware.
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