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Development of software for the White Rabbit switch, and in particular the embedded Linux system running in the ARM9 processor. More info at the Wiki page

White Rabbit PTP Core software for LatticeMico32. It consists of a software wrapper for running a PTP daemon without an operating system and device drivers for WRPC HDL internals.

A Precise Time Protocol (PTP, IEEE 1588) software stack whose single source code can be compiled for many architectures (POSIX systems, WR switch, WR node, ...) and which is easily extensible.

Production and functional tests for FMC TDC 1ns 5cha.

A USB controlled switch box with 1 to 4 switching. Can send out a reference voltage. Multiple configurations possible. Used for the calibration of ADC, TDC and Fine delay mezzanines. More info at the Wiki page

A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.

More info at the Wiki page

A fully open electronic watch project featuring an integrated GPS receiver. More info at the Wiki page

BabyWR is a general purpose small pluggable WR node in a M.2 form-factor. More info at the Wiki page

White Rabbit is a fully deterministic Ethernet-based network for general purpose data transfer and synchronization. It can synchronize over 1000 nodes with sub-ns accuracy over fiber lengths of up to 10 km. Commercially available. More info at the Wiki page

Active 32/64 channels 19" patch panel for FPGA boards, with robust 5V TTL I/Os, configurable through I²C and USB-C. More info at the Wiki page

Firmware(gateware) for FPGA on AIDA-Innova TLU ( AIDAInnova_TLU )

Production and functional tests for PXIe controller COM Express based. More info at the Wiki page

FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os on LEMO 00 connectors are TTL compatible. Commercially available. More info at the Wiki page

White Rabbit Trigger Distribution project. More info at the Wiki page

The VFC is a VME carrier for two VITA 57 (FMC) mezzanines. For more details please refer to the wiki pages. Obsolete project. Replaced by VFC-HD.

A fine delay generator in FMC format with 1 input and 4 outputs. The resolution is 1 ns. Commercially available. More info at the Wiki page

Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet.

This project defines data structures, to be embedded in the FPGA memory address space, to enumerate the devices that have been synthetized in the current design. The same structure is also used as a simple flash file system. AKA Self-Describing Bus (SDB) Specification for Logic Cores. The layout is simple enough to be parsed both by the host and by the internal soft-core, if any.

The documentation is public, and related code is GNU GPL licensed.

Software support for the SPEC board, including kernel and user-space Linux code. The package also include the fmc-bus driver, which is expected to be used by other carriers as well.

A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.

The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.