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IPBus is a FPGA Core that controls a Wishbone bus via Ethernet. Currently the transport protocol is UDP/IP, although there are plans for an ATA over Ethernet (AoE) implementation. There are reference designs for the SP601 and SP605 Xilinx FPGA boards.
Details at http://ipbus.web.cern.ch/ipbus/
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SPI Boards Package is a set of electronic boards developed at Soleil Synchrotron (France). These boards can be connected together in a daisy chain and they communicate with an embedded controller via an SPI Bus. They provide the following features:
- Platform allowing us to build specific solutions with simple and open tools.
- Modular architecture.
- Provide solutions for applications which require synchronization.
- Low level process implementation to achieve better performance. - Easy Control network connection
The main CPU board contains a microprocessor. It manages a task for communication with the supervision, an embedded process and SPI communication with the peripheral boards. We have a modular approach that means we can make various Peripheral board combinations between 16-bit DAC, 16-bit ADC, and a calculator board for motor encoder.
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An HPC FMC with 4 Digital to Analog Converter channels working at 250 MS/s with 16-bit resolution.
More information on the wiki page The design is currently used only for the CERN RF-group purposesUpdated -
A card used in CERN's Linac 3 for the control of the electromagnetic field inside RF accelerating cavities.
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A transparent Wishbone bridge between two FPGAs using high-speed serial links. This project is on hold.* More info at the Wiki page
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A Virtex6-based optical link interface AMC equipped with SFP+ and FMC sockets
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RHINO (Reconfigurable Hardware Interface for computiNg and radiO) is a compute platform consisting of a FPGA element with dedicated memory, high speed communication, and FMC-LPC (Vita 57.1) IO expansion slots, all controlled via an ARM Cortex A8 processor running the BORPH operating system.
For progress updates, follow us on twitter @rhinoplatform
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A High Pin Count FMC carrier in VXS format with two Virtex 5 FPGAs plus a DSP on board.
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A converter between USB/Ethernet and WorldFIP, allowing the bus arbitration and control of a WorldFIP fieldbus segment from a USB or Ethernet-equipped computer.
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The level conversion board project hosts a set of boards in VME form factor, with additional remote diagnostics/monitoring via I2C.
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OpenPicus is an Italian project made to fill the gap between Embedded Low Cost and Wireless. Picus modules are based on the well known Microchip PIC 24F 16bit processor connected to a Wireless Transceiver (WI-FI or BLUETOOTH). The OpenPicus Framework let you develop your Apps in easy way even without specific experience with Communication protocols. The IDE is also FREE and you can create, compile and download to the modules yoru Apps, no programming tools are needed.
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pcie-fmc-soc-vdas is a PCIe carrier for a high pin count FPGA Mezzanine Card (VITA 57). The main component is a SOC chip used in cellular base stations that can do advanced processing. More info at the Wiki page
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FMC nanoFIP is an interface card for the WorldFIP network in an LPC FMC form-factor. More info at the Wiki page
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VME projects are sub-projects of this ohwr project. See all sub-projects for more information.
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Utility project for the CERN BE-CO-HT Continuous Integration (CI) infrastructure.
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