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  • We have designed an FPGA Mezzanine card (standard FMC/Vita 57) for high-channel-count electrophysiology, with 128 channels (potentially up to 512), based upon Intan Tech's RHA2132 (2 uV rms input-referred noise), sampled at 25kHz 18bit by AD7982. We are basing our design on the reference design provided by Reid Harrison of Intan Tech for their 16-channel evaluation board. The expected cost of the device should be under 5000$.

    In order to have an integrated solution we intend to have as default carrier the Opal Kelly Shuttle LX1, an inexpensive USB FMC carrier with an excellent USB controller. The integrated solution will be completed with software on the PC side to grab to disk continuously and/or display in some fashion all 128 channels.

    Our status: We have an alpha card. It has passed most tests---we can grab from any channel at 1MS/s. We have an alpha microcode: it grabs from any channel and stores on the PC.

    Our current team: Marcelo Magnasco (Rockefeller University, New York), design. Andres Cicuttin (ICTP, Trieste), schematics + fpga Maria Liz Crespo (ICTP, Trieste), fpga Sanjee Abeytunge (MSKCC, New York) layout Nicholas Joseph (RU) Macintosh drivers

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  • PHASE (Portable Hardware Analyzer with Sharing Explorer) aims at unifying hardware debugging in a single tool. From the host machine, a user may graphically interconnect components to describe the connection between his computer and the target device to debug. For example, a USB JTAG cable might be the root node, connected to an Arria2 development board with a CPLD and an FPGA, containing a LM32 processor.

    Wherever possible, PHASE fetches design descriptions from the internet based on the detected JTAG IDCODEs, USB vendor IDs, or PnP BUS information. In the preceding example, each step of the chain would be automatically detected. The USB cable from the vendor+product codes, the FPGA from the JTAG IDCODE and the LM32 from the Arria2's sld hub. The user would now be presented with read/write access to the data and instruction buses for visual inspection or firmware loading. Furthermore, the user could launch gdb to halt and single-step the embedded LM32 CPU.

    If a device is not yet described, the user may assemble a driver out of the reusable software components. For example, an Altera USB-Blaster driver is just a FTDI device chained with a byte packeter and a JTAG bit banger. Once the design has been graphically assembled, it is automatically scanned for attached JTAG devices and the USB cable design is shared online with any future users of the same cable.

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  • OpenPicus is an Italian project made to fill the gap between Embedded Low Cost and Wireless. Picus modules are based on the well known Microchip PIC 24F 16bit processor connected to a Wireless Transceiver (WI-FI or BLUETOOTH). The OpenPicus Framework let you develop your Apps in easy way even without specific experience with Communication protocols. The IDE is also FREE and you can create, compile and download to the modules yoru Apps, no programming tools are needed.

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  • RHINO (Reconfigurable Hardware Interface for computiNg and radiO) is a compute platform consisting of a FPGA element with dedicated memory, high speed communication, and FMC-LPC (Vita 57.1) IO expansion slots, all controlled via an ARM Cortex A8 processor running the BORPH operating system.

    For progress updates, follow us on twitter @rhinoplatform

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  • An FMC board with an analog 125 MS/s input and an analog 600 MS/s output for RF applications.

    More info at the Wiki page
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  • Gateware (HDL design) for nanoFIP.

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  • Project holding machines and mechanical hardware tools as subproject.

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  • Projects / FMC DEL 1ns 4cha - stand-alone application

    GNU General Public License v3.0 only

    A fully operational stand-alone FMC Delay card based White-Rabbit node which can be initialized and perform periodic calibrations without requiring to be plugged on a PC, reducing final system cost, size and power consumption. More info at the Wiki page

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  • Gateware (HDL design) for MasterFIP.

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  • A cute-wr is a compact WR-node implementation with minimum components required. The initial design is derived from SPEC, but would work in an opposite manner as a FMC wr-nic, providing 2 DIO channels, external CLK input, EEPROM, JTAG, RS232, and expandable IOs through FMC connector. The gateware and software of cute-wr would also keep maximum compatibility with SPEC. Project is obsolete. See cute-wr-dp for a similar board.

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  • Common gateware for the different level conversion circuits.

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  • 4-channel 16-bit 250 MS/s (700 MHz analog input bandwidth) ADC (ISLA216P25) FMC module.

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  • A simple card that measures temperatures using low cost external Silicon sensors (just ordinary bipolar transistors). On the front panel it has 8 mini-jack connectors to quickly rearrange the setup. We use this kind of the cards for measurement of the temperature distribution of key components on PCBs. The card has also application in our GEM detector readout system to monitor temperatures inside the detector box - it is attached to the rear transition module with an FMC connector. The card uses only an I2C interface which can be connected to the I2C bus of the card or to the LA lanes.

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  • Project holding Data centre environmental sensor projects. E.g. measuring humidity, dust, temperature etc.

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  • Sub-micrometer resolution beam position monitoring system (BPM) for accelerators. It provides real-time orbit monitoring, buffered data readouts, fast orbit feedback capabilities and advanced beam diagnostics tools.

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  • Local image descriptors are calculated for every 800x600 image up to 36 fps. All implemented in Handel-C, they provide energy with unsigned 8 bit fixed-point precision, as well as phase and orientation with Q7.2. The implementation is based on a multi-oriented bank of Gabor filters.

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  • Neo51 is an open source hardware based on 89V51 microcontroller. It has a dual mode feature selectable via DIP switch supporting arduino hardware compatible ports and the legacy 8051 ports.

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  • A project to host all software and hardware developments related to testing the White Rabbit switch.

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  • nanoFIPdiag is a WorldFIP node dedicated to monitoring and diagnostics. It uses the nanoFIP chip in stand-alone mode and echoes the received data (through hardwired contacts it copies the received payload to the produced one). The module is designed to be radiation-tolerant

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