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The programmable bench power supply project was an attempt to create reliable, modular, open and programmable power supply. Various voltage single range operation (i.e. 0 – 30 V, 0 – 40 V or 0 – 50 V per channel). Various current single range operation (i.e. 0 – 3 A or 0 – 5 A per channel)
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The PFC is a 4-lane PCIe carrier for a single VITA 57 (FMC) mezzanine. It has many memory and clocking resources and supports the White Rabbit timing and control network. For more details please refer to the Wiki pages. *Warning. This project is on hold. Refer to the SPEC*
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Software to support the FMC ADC 130M 16B 4CH mezzanine, including: configuration application and HDL firmware, with functionality for data acqusition. For use with FCS application. More info at the Wiki page
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The Dual AMC carrier enables stand-alone operation of an AMC FMC carrier or any other AMC board. It has 4 SFP connectors, 2 QSFP cages, 8 trigger I/O routed to the MLVDS ports and power entry. Two versions, allowing the use of a RTM or not. More info at the Wiki page
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Software to support the FMC DIO 32CH TTL A mezzanine, including: configuration application and HDL firmware, with functionality for data acqusition. For use with FCS application. More info at the Wiki page
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This project guides new users to start in the White Rabbit “World” with simple experiments. The starting kit uses two SPEC + FMC-DIO cards. Each node allows basic operations such as input timestamping or programmable output pulse generation. Additionally, specific software and gateware layers allow to use it as a standard network interface card implementing the White Rabbit technology functionalities.
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Programmable attenuator of RF signals with very high voltage range (50mV – 1000 V) for protecting digitizers against damage by high voltage signals. Four channels with SMA connectors; Three attenuation values: 0, -20, -40 dB; Bandwidth: DC – 2 GHz.
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Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet.
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A software suite written in Python to help with production tests of PCBs. AKA PTS.
%(red)This pts-base project is used to re-organise the current pts project In the future this project will replace the existing pts project.
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E-bone first aims at interfacing an FPGA based PCIe Endpoint core to a collection of other cores. The E-bone release contains a number of general purpose cores within that scope. E-bone specifications cater for both a Control Interconnect and a Fast Transmitter. The Control Interconnect defines a 32 bit wide interconnection between a number of masters and slaves. The Fast Transmitter is a one way path (up to 256 bit wide) aiming at dumping large data sets to the root complex. E-bone is nevertheless not restricted to PCIe interfacing and may be used for developing sub-systems in others environments.
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hdl-core-lib / wishbone-gen
Affero General Public License v1.0READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS
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SDB (Self-describing Bus) allows to enumerate the cores that are live in the current FPGA binary, either from the host computer or from the internal soft-core CPU in the FPGA itself. The project provides the software support and the specification. More info at the Wiki page
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The level conversion board project hosts a set of boards in VME form factor, with additional remote diagnostics/monitoring via I2C.
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Software to support the PandABox is common between all platforms using the PandABlocks framework and is developed on Github:
PandABlocks-rootfs: Github repository for building onboard rootfs from source PandABlocks-server: Github repository for onboard TCP server PandABlocks-webserver: Github repository for onboard webserver PandABlocks-client: Github repository for Python client side tools ADPandABlocks: Github repository for EPICS areaDetector driver
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PandA Motion Project is a collaboration between SOLEIL and DIAMOND to upgrade their “Position and Acquisition” processing platform. PandA will provide a common encoder processing platform based on Zynq 7030 and supporting multiple encoder standards (incremental, SSI, BISS...). It will deliver synchronous triggering and data capture capabilities.
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A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.
The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.
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