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FMC prototype board fmc-prt-lpc is providing means to develop FMC systems for later integration to standard FMC Low-Pin Count form factor. Breadboard area connecting LPC pins. More info at the Wiki page

VME projects are sub-projects of this ohwr project. See all sub-projects for more information.

Study of the “Open Hardware Initiative” at CERN with a focus on the technologies of participation that were mobilized to assemble critical infrastructure for basic research in high energy physics.

The DAPHNE front end board is a piece of hardware that digitizes the output signal from one of the systems of the far detector in the DUNE experiment. For more information, see the wiki

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SDB (Self-describing Bus) allows to enumerate the cores that are live in the current FPGA binary, either from the host computer or from the internal soft-core CPU in the FPGA itself. The project provides the software support and the specification. More info at the Wiki page

A simple 4-lane PXIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. Commercially available. Labview driver available for Fine Delay and TDC mezzanines. More info at the Wiki page

FMC thermocouple card interfacing with zQSFP+ to samc-temp-thcpl-20ch which connects 20 single-ended K-type or N-type thermocouple channels. Used in SAMbuCa project. More info at the Wiki page

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Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

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Tester board to test PXIe processor modules. Two variants: slot 2 and slot 10 (system timing slot). More info at the Wiki page

VHDL coding style document to be used at ohwr.org The project contains also a tool to automatically check the coding style. More info at the Wiki page

Projects that fit in 19 inch racks. Also known as pizza-box projects.

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READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

Collection of WRTD reference designs provided by (and used at) CERN