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A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor.

This project presents an FPGA architecture for the computation of visual attention based on the combination of a bottom-up saliency and a top-down task-dependent modulation streams. The bottom-up stream is deployed including optical flow, local energy, red-green and blue-yellow color opponencies, and different local orientation maps. The final saliency is modulated by two highlevel features: optical flow and disparity. The architecture include some feedback masks to adapt the weights of the features that are part of the bottom-up stream, depending on the specific target application. The target applications are ADAS (Advanced Driving Assistance Systems), video surveillance, robotics, etc...

FmcAdc200k16b11cha is an 11 channel 200kSPS 16 bit ADC card in FMC (FPGA Mezzanine Card) standard. The input voltage range is settable to /-10V or/-5V. The input impedance is 1MOhm.

The dual channel L band front-end consist of a FMC dual channel L band down-converter, preamplifiers and duplex filters. Each IQ down-converter has a wide adjustable bandwidth (>100 MHz), adjustable gain and two 250MHz 8 bits or 160 MHZ 12 bits or 105MHZ 14 bits multi-mode ADC's. The down-converter mode is switchable: single receiving frequency band for both channels, or dual frequency band: each channel has its own receiving frequency band. For GNSS its includes timing support, Other applications are radio astronomy and microwave digitizing back-end.

The level conversion board project hosts a set of boards in VME form factor, with additional remote diagnostics/monitoring via I2C.

The differential to single ended cable driver is an active electronics circuit that implements a high-current differential receiver, with optional attenuation (0dB, 6dB, 10dB and 12dB available), polarity inversion and ground lifting on input and output. More info at the Wiki page

wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:

- Automatically allocated memory layout

- VHDL/Verilog code for the slave module

- C header files for driver development - Nice HTML documentation

Read the wbgen2-Documentation Get the latest version binaries https://www.ohwr.org/attachments/5659/wbgen2-bin.tar.bz2

This library provides a generic API for ADC devices, so that applications can use this API to access any of the supported ADC boards. Currently the library supports the following boards:

fmc-adc-100m14b14cha

For testing and debugging purpose it supports also a couple of virtual boards that you can use to start the development of your application.

More info at the Wiki page

A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor. Software.

READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

The TimIQ system is an IQ modulator allowing to phase shift a radio frequency clock with a resolution of 40 fs and an accuracy of 8 ps. Hardware.

An HPC FMC with 4 Digital to Analog Converter channels working at 250 MS/s with 16-bit resolution.

More information on the wiki page The design is currently used only for the CERN RF-group purposes

READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor. Testing.

READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

The OpenDSO is a bench top oscilloscope, built on top of an extensible Zynq-based platform. Features: 2x100 MS/s (basic frontend), extendable to 4x1GS/s or 2x2GS/s; Zynq 7000 FPGA, 512 MB RAM; 8" multitouch display with Qt GUI

READ-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS

A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.