Checking in files after generating artwork for power filter. Some files to check in after desparate struggle to produce artwork for main board

Ran constraints manager from HDL capture. Didn't resolve DRC issue. Eventually fixed. Looks like I have a Physical Constraint set and an Electrical constraint set with the same name. One with tighter constraints was over-ruling the other. However, error message reported the limit from the non-failing one. Starting layout of production artwork. Components placed. Connections made. Dangling lines/vias fixed. Need to produce silk

Started routing ADCs. 4 digital side , 3 analogue side routed so far. Had to edit schematic slightly to uncross lines

Minor bug-fixes on schematic to sort out problems with connection from DIN connectors to ADCs. Did a trial placement of ADCs.