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euro-adc-65m-14b-40cha-gw
Commit f98014ca authored by Dan Saunders's avatar Dan Saunders
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fixing merges

parents 03269619 a1628f5b
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Showing with 2436 additions and 208 deletions
boards/pc051a/base_fw/synth/firmware/hdl/pc051a_infra.vhd
View file @ f98014ca
......@@ -23,6 +23,8 @@ entity pc051a_infra is
clk125_o: out std_logic;
rst125_o: out std_logic;
clk200: out std_logic; -- 200MHz unbuffered clock for IDELAYCTRL
pllclk: out std_logic;
pllrefclk: out std_logic;
nuke: in std_logic; -- The signal of doom
soft_rst: in std_logic; -- The signal of lesser doom
leds: out std_logic_vector(1 downto 0); -- status LEDs
......@@ -98,6 +100,8 @@ begin
sfp_los => sfp_los,
clk125_out => clk125,
clk125_fr => clk125_fr,
pllclk_out => pllclk,
pllrefclk_out => pllrefclk,
rsti => rst_eth,
locked => eth_locked,
tx_data => mac_tx_data,
......
boards/pc051a/base_fw/synth/firmware/hdl/top_pc051a.vhd
View file @ f98014ca
......@@ -60,6 +60,7 @@ end top;
architecture rtl of top is
signal clk_ipb, rst_ipb, clk125, rst125, nuke, soft_rst, userled, clk200, stealth_mode: std_logic;
signal pllclk, pllrefclk: std_logic;
signal ipb_out: ipb_wbus;
signal ipb_in: ipb_rbus;
signal debug: std_logic_vector(3 downto 0);
......@@ -84,6 +85,8 @@ begin
clk125_o => clk125,
rst125_o => rst125,
clk200 => clk200,
pllclk => pllclk,
pllrefclk => pllrefclk,
nuke => nuke,
soft_rst => soft_rst,
leds => infra_leds,
......@@ -111,6 +114,8 @@ begin
clk125 => clk125,
rst125 => rst125,
clk200 => clk200,
pllclk => pllclk,
pllrefclk => pllrefclk,
nuke => nuke,
soft_rst => soft_rst,
stealth_mode => stealth_mode,
......
boards/pc051a/base_fw/synth/firmware/ucf/pc051a.tcl
View file @ f98014ca
......@@ -29,6 +29,8 @@ set_property PACKAGE_PIN F6 [get_ports eth_clk_p]
set_property PACKAGE_PIN E6 [get_ports eth_clk_n]
set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hier -filter {name=~infra/eth/*/gtpe2_i}]
set_property LOC GTPE2_CHANNEL_X0Y6 [get_cells -hier -filter {name=~*/mgt_ds/*/gtpe2_i}]
set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells -hier -filter {name=~*/mgt_us/*/gtpe2_i}]
proc false_path {patt clk} {
set p [get_ports -quiet $patt -filter {direction != out}]
......
boards/pc051b/base_fw/synth/firmware/hdl/pc051b_infra.vhd
View file @ f98014ca
......@@ -23,6 +23,8 @@ entity pc051b_infra is
clk125_o: out std_logic;
rst125_o: out std_logic;
clk200: out std_logic; -- 200MHz unbuffered clock for IDELAYCTRL
pllclk: out std_logic;
pllrefclk: out std_logic;
nuke: in std_logic; -- The signal of doom
soft_rst: in std_logic; -- The signal of lesser doom
leds: out std_logic_vector(1 downto 0); -- status LEDs
......@@ -98,6 +100,8 @@ begin
sfp_los => sfp_los,
clk125_out => clk125,
clk125_fr => clk125_fr,
pllclk_out => pllclk,
pllrefclk_out => pllrefclk,
rsti => rst_eth,
locked => eth_locked,
tx_data => mac_tx_data,
......
boards/pc051b/base_fw/synth/firmware/hdl/top_pc051b.vhd
View file @ f98014ca
......@@ -44,6 +44,7 @@ end top;
architecture rtl of top is
signal clk_ipb, rst_ipb, clk125, rst125, nuke, soft_rst, userled, clk200, stealth_mode: std_logic;
signal pllclk, pllrefclk: std_logic;
signal ipb_out: ipb_wbus;
signal ipb_in: ipb_rbus;
signal debug: std_logic_vector(3 downto 0);
......@@ -70,6 +71,8 @@ begin
clk125_o => clk125,
rst125_o => rst125,
clk200 => clk200,
pllclk => pllclk,
pllrefclk => pllrefclk,
nuke => nuke,
soft_rst => soft_rst,
leds => infra_leds,
......@@ -93,6 +96,8 @@ begin
clk125 => clk125,
rst125 => rst125,
clk200 => clk200,
pllclk => pllclk,
pllrefclk => pllrefclk,
nuke => nuke,
soft_rst => soft_rst,
stealth_mode => stealth_mode,
......
boards/pc051b/base_fw/synth/firmware/ucf/pc051b.tcl
View file @ f98014ca
......@@ -24,6 +24,8 @@ set_property PACKAGE_PIN F6 [get_ports eth_clk_p]
set_property PACKAGE_PIN E6 [get_ports eth_clk_n]
set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hier -filter {name=~infra/eth/*/gtpe2_i}]
set_property LOC GTPE2_CHANNEL_X0Y6 [get_cells -hier -filter {name=~*/mgt_ds/*/gtpe2_i}]
set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells -hier -filter {name=~*/mgt_us/*/gtpe2_i}]
proc false_path {patt clk} {
set p [get_ports -quiet $patt -filter {direction != out}]
......
components/solid/addr_table/sc_chan.xml
View file @ f98014ca
......@@ -6,7 +6,6 @@
<node id="invert" mask="0x4"/>
<node id="mode" mask="0x10"/>
<node id="src" mask="0xc0"/>
<node id="zs_thresh" mask="0x3fff0000"/>
</node>
<node id="stat" address="0x1">
<node id="cap_full" mask="0x1"/>
......@@ -14,6 +13,8 @@
<node id="dr_full" mask="0x4"/>
<node id="dr_warn" mask="0x8"/>
<node id="err" mask="0x10"/>
<node id="slip" mask="0xff00"/>
<node id="tap" mask="0x1f0000"/>
</node>
</node>
<node id="buf" address="0x2" description="channel buffers" fwinfo="endpoint;width=1">
......@@ -23,15 +24,15 @@
<node id="zs_thresh" address="0x4" mode="block" size="0x4" description="zero suppression thresholds" fwinfo="endpoint;width=2"/>
<node id="trig_thresh" address="0x8" description="trigger thresholds" fwinfo="endpoint;width=2">
<node id="threshold" address="0x0">
<node id="thresh" mask="0x3ff"/>
<node id="thresh" mask="0x3fff"/>
</node>
<node id="neutronpeaks" address="0x1">
<node id="pthresh" mask="0x3ff"/>
<node id="pthresh" mask="0x3fff"/>
<node id="cthresh" mask="0x1ff0000"/>
<node id="wsize" mask="0xf0000000"/>
</node>
<node id="neutronsamples" address="0x2">
<node id="pthresh" mask="0x3ff"/>
<node id="pthresh" mask="0x3fff"/>
<node id="cthresh" mask="0x1ff0000"/>
<node id="wsize" mask="0xf0000000"/>
</node>
......
components/solid/addr_table/sc_daq.xml
View file @ f98014ca
......@@ -3,7 +3,7 @@
<node id="timing" address="0x10" module="file://sc_timing.xml"/>
<node id="fake" address="0x20" module="file://sc_fake.xml"/>
<node id="rtrig" address="0x28" module="file://sc_rtrig.xml"/>
<node id="tlink" address="0x30" fwinfo="endpoint;width=0"/>
<node id="tlink" address="0x30" module="file://sc_trig_link.xml"/>
<node id="trig" address="0x40" module="file://sc_trig.xml"/>
<node id="roc" address="0x60" module="file://sc_roc.xml"/>
<node id="roc" address="0x80" module="file://sc_roc.xml"/>
</node>
components/solid/addr_table/sc_fake.xml
View file @ f98014ca
......@@ -13,8 +13,8 @@
<node id="samp" mask="0xff000000"/>
</node>
<node id="size" address="0x1">
<node id="level" mask="0x3ff"/>
<node id="ped" mask="0x3ff0000"/>
<node id="level" mask="0x3fff"/>
<node id="ped" mask="0x3fff0000"/>
</node>
</node>
</node>
components/solid/addr_table/sc_timing.xml
View file @ f98014ca
......@@ -9,15 +9,13 @@
<node id="pipeline_en" mask="0x20"/>
<node id="send_sync" mask="0x40"/>
<node id="chan_slip" mask="0x1000"/>
<node id="chan_rst_buf" mask="0x2000"/>
<node id="chan_cap" mask="0x4000"/>
<node id="chan_inc" mask="0x8000"/>
<node id="chan_cap" mask="0x2000"/>
<node id="chan_inc" mask="0x4000"/>
<node id="zs_blks" mask="0xff0000"/>
</node>
<node id="stat" address="0x8">
<node id="wait_sync" mask="0x1"/>
<node id="sync_err" mask="0x2"/>
<node id="io_err" mask="0x4"/>
<node id="locked" mask="0x8"/>
</node>
<node id="sctr_l" address="0x9"/>
<node id="sctr_h" address="0xa"/>
......
components/solid/addr_table/sc_trig.xml
View file @ f98014ca
......@@ -12,11 +12,12 @@
</node>
</node>
<node id="loc_mask" address="0x4" description="local trigger generator" fwinfo="endpoint;width=0"/>
<node id="zs_cfg" address="0x5" description="ZS threshold selection" fwinfo="endpoint;width=0"/>
<node id="dtmon" address="0x6" description="deadtime monitor buffer" fwinfo="endpoint;width=1">
<node id="hop_cfg" address="0x5" description="hop count control" fwinfo="endpoint;width=0"/>
<node id="zs_cfg" address="0x6" description="ZS threshold selection" fwinfo="endpoint;width=0"/>
<node id="dtmon" address="0x8" description="deadtime monitor buffer" fwinfo="endpoint;width=1">
<node id="addr" address="0x0"/>
<node id="data" address="0x1" mode="port"/>
</node>
<node id="seq" address="0x8" module="file://sc_seq.xml"/>
<node id="masks" address="0x10" mode="block" size="0x10" description="channel trigger masks" fwinfo="endpoint;width=4"/>
<node id="seq" address="0x10" module="file://sc_seq.xml"/>
<node id="masks" address="0x20" mode="block" size="0x10" description="channel trigger masks" fwinfo="endpoint;width=4"/>
</node>
components/solid/addr_table/sc_trig_link.xml 0 → 100644
View file @ f98014ca
<node id="tlink" description="Inter-plane serial links" fwinfo="endpoint;width=2">
<node id="ctrl" address="0x0">
<node id="en_us" mask="0x1"/>
<node id="en_ds" mask="0x2"/>
<node id="rst_tx" mask="0x4"/>
<node id="rst_rx" mask="0x8"/>
<node id="loop_us" mask="0x70"/>
<node id="loop_ds" mask="0x380"/>
</node>
<node id="us_stat" address="0x2">
<node id="rdy_tx" mask="0x1"/>
<node id="rdy_rx" mask="0x2"/>
<node id="buf_tx" mask="0xc"/>
<node id="buf_rx" mask="0x70"/>
<node id="stat_tx" mask="0x300"/>
<node id="stat_rx" mask="0x7c00"/>
<node id="remote_id" mask="0xff0000"/>
</node>
<node id="ds_stat" address="0x3">
<node id="rdy_tx" mask="0x1"/>
<node id="rdy_rx" mask="0x2"/>
<node id="buf_tx" mask="0xc"/>
<node id="buf_rx" mask="0x70"/>
<node id="stat_tx" mask="0x300"/>
<node id="stat_rx" mask="0x7c00"/>
<node id="remote_id" mask="0xff0000"/>
</node>
</node>
components/solid/firmware/cfg/sc_daq_sim.dep
View file @ f98014ca
src sc_daq.vhd
src ipbus_decode_sc_daq.vhd
addrtab -t sc_daq.xml
include sc_timing_sim.dep sc_fake.dep sc_chan.dep sc_trig.dep sc_trig_link.dep sc_roc.dep sc_rtrig.dep
include sc_timing_sim.dep sc_fake.dep sc_chan.dep sc_trig.dep sc_trig_link_sim.dep sc_roc.dep sc_rtrig.dep
src -c ipbus-firmware:components/ipbus_util led_stretcher.vhd ipbus_clock_div.vhd
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
components/solid/firmware/cfg/sc_trig_link.dep
View file @ f98014ca
src sc_trig_link.vhd
src sc_trig_link.vhd sc_trig_mgt_wrapper.vhd sc_trig_link_pipe.vhd
addrtab sc_trig_link.xml
src ../cgn/sc_trig_link_mgt.xci
src -c ipbus-firmware:components/ipbus_slaves ipbus_ctrlreg_v.vhd ipbus_reg_types.vhd
components/solid/firmware/cfg/sc_trig_link_sim.dep 0 → 100644
View file @ f98014ca
src sc_trig_link.vhd ../sim_hdl/sc_trig_mgt_sim.vhd sc_trig_link_pipe.vhd
addrtab sc_trig_link.xml
src -c ipbus-firmware:components/ipbus_slaves ipbus_ctrlreg_v.vhd ipbus_reg_types.vhd
components/solid/firmware/cgn/sc_trig_link_mgt.xci 0 → 100644
View file @ f98014ca
This source diff could not be displayed because it is too large. You can view the blob instead.
components/solid/firmware/hdl/ipbus_decode_sc_daq.vhd
View file @ f98014ca
......@@ -17,7 +17,7 @@ package ipbus_decode_sc_daq is
subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
function ipbus_sel_sc_daq(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-- START automatically generated VHDL the Thu Oct 19 13:25:12 2017
-- START automatically generated VHDL the Tue Nov 14 21:11:12 2017
constant N_SLV_CHAN: integer := 0;
constant N_SLV_TIMING: integer := 1;
constant N_SLV_FAKE: integer := 2;
......@@ -37,21 +37,21 @@ package body ipbus_decode_sc_daq is
variable sel: ipbus_sel_t;
begin
-- START automatically generated VHDL the Thu Oct 19 13:25:12 2017
if std_match(addr, "-------------------------000----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CHAN, IPBUS_SEL_WIDTH)); -- chan / base 0x00000000 / mask 0x00000070
elsif std_match(addr, "-------------------------001----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TIMING, IPBUS_SEL_WIDTH)); -- timing / base 0x00000010 / mask 0x00000070
elsif std_match(addr, "-------------------------0100---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_FAKE, IPBUS_SEL_WIDTH)); -- fake / base 0x00000020 / mask 0x00000078
elsif std_match(addr, "-------------------------0101---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_RTRIG, IPBUS_SEL_WIDTH)); -- rtrig / base 0x00000028 / mask 0x00000078
elsif std_match(addr, "-------------------------0110---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TLINK, IPBUS_SEL_WIDTH)); -- tlink / base 0x00000030 / mask 0x00000078
elsif std_match(addr, "-------------------------10-----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TRIG, IPBUS_SEL_WIDTH)); -- trig / base 0x00000040 / mask 0x00000060
elsif std_match(addr, "-------------------------11-----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_ROC, IPBUS_SEL_WIDTH)); -- roc / base 0x00000060 / mask 0x00000060
-- START automatically generated VHDL the Tue Nov 14 21:11:12 2017
if std_match(addr, "------------------------0000----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CHAN, IPBUS_SEL_WIDTH)); -- chan / base 0x00000000 / mask 0x000000f0
elsif std_match(addr, "------------------------0001----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TIMING, IPBUS_SEL_WIDTH)); -- timing / base 0x00000010 / mask 0x000000f0
elsif std_match(addr, "------------------------00100---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_FAKE, IPBUS_SEL_WIDTH)); -- fake / base 0x00000020 / mask 0x000000f8
elsif std_match(addr, "------------------------00101---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_RTRIG, IPBUS_SEL_WIDTH)); -- rtrig / base 0x00000028 / mask 0x000000f8
elsif std_match(addr, "------------------------00110---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TLINK, IPBUS_SEL_WIDTH)); -- tlink / base 0x00000030 / mask 0x000000f8
elsif std_match(addr, "------------------------01------") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TRIG, IPBUS_SEL_WIDTH)); -- trig / base 0x00000040 / mask 0x000000c0
elsif std_match(addr, "------------------------100-----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_ROC, IPBUS_SEL_WIDTH)); -- roc / base 0x00000080 / mask 0x000000e0
-- END automatically generated VHDL
else
......
components/solid/firmware/hdl/ipbus_decode_sc_trig.vhd
View file @ f98014ca
......@@ -17,14 +17,15 @@ package ipbus_decode_sc_trig is
subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
function ipbus_sel_sc_trig(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-- START automatically generated VHDL the Wed Aug 23 15:54:14 2017
-- START automatically generated VHDL the Tue Nov 14 21:11:13 2017
constant N_SLV_CSR: integer := 0;
constant N_SLV_LOC_MASK: integer := 1;
constant N_SLV_ZS_CFG: integer := 2;
constant N_SLV_DTMON: integer := 3;
constant N_SLV_SEQ: integer := 4;
constant N_SLV_MASKS: integer := 5;
constant N_SLAVES: integer := 6;
constant N_SLV_HOP_CFG: integer := 2;
constant N_SLV_ZS_CFG: integer := 3;
constant N_SLV_DTMON: integer := 4;
constant N_SLV_SEQ: integer := 5;
constant N_SLV_MASKS: integer := 6;
constant N_SLAVES: integer := 7;
-- END automatically generated VHDL
......@@ -36,19 +37,21 @@ package body ipbus_decode_sc_trig is
variable sel: ipbus_sel_t;
begin
-- START automatically generated VHDL the Wed Aug 23 15:54:14 2017
if std_match(addr, "---------------------------000--") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000000 / mask 0x0000001c
elsif std_match(addr, "---------------------------00100") then
sel := ipbus_sel_t(to_unsigned(N_SLV_LOC_MASK, IPBUS_SEL_WIDTH)); -- loc_mask / base 0x00000004 / mask 0x0000001f
elsif std_match(addr, "---------------------------00101") then
sel := ipbus_sel_t(to_unsigned(N_SLV_ZS_CFG, IPBUS_SEL_WIDTH)); -- zs_cfg / base 0x00000005 / mask 0x0000001f
elsif std_match(addr, "---------------------------0011-") then
sel := ipbus_sel_t(to_unsigned(N_SLV_DTMON, IPBUS_SEL_WIDTH)); -- dtmon / base 0x00000006 / mask 0x0000001e
elsif std_match(addr, "---------------------------01---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_SEQ, IPBUS_SEL_WIDTH)); -- seq / base 0x00000008 / mask 0x00000018
elsif std_match(addr, "---------------------------1----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_MASKS, IPBUS_SEL_WIDTH)); -- masks / base 0x00000010 / mask 0x00000010
-- START automatically generated VHDL the Tue Nov 14 21:11:13 2017
if std_match(addr, "--------------------------0000--") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000000 / mask 0x0000003c
elsif std_match(addr, "--------------------------000100") then
sel := ipbus_sel_t(to_unsigned(N_SLV_LOC_MASK, IPBUS_SEL_WIDTH)); -- loc_mask / base 0x00000004 / mask 0x0000003f
elsif std_match(addr, "--------------------------000101") then
sel := ipbus_sel_t(to_unsigned(N_SLV_HOP_CFG, IPBUS_SEL_WIDTH)); -- hop_cfg / base 0x00000005 / mask 0x0000003f
elsif std_match(addr, "--------------------------000110") then
sel := ipbus_sel_t(to_unsigned(N_SLV_ZS_CFG, IPBUS_SEL_WIDTH)); -- zs_cfg / base 0x00000006 / mask 0x0000003f
elsif std_match(addr, "--------------------------00100-") then
sel := ipbus_sel_t(to_unsigned(N_SLV_DTMON, IPBUS_SEL_WIDTH)); -- dtmon / base 0x00000008 / mask 0x0000003e
elsif std_match(addr, "--------------------------011---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_SEQ, IPBUS_SEL_WIDTH)); -- seq / base 0x00000018 / mask 0x00000038
elsif std_match(addr, "--------------------------10----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_MASKS, IPBUS_SEL_WIDTH)); -- masks / base 0x00000020 / mask 0x00000030
-- END automatically generated VHDL
else
......
components/solid/firmware/hdl/sc_chan.vhd
View file @ f98014ca
......@@ -12,9 +12,6 @@ use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.VComponents.all;
use work.ipbus.all;
use work.ipbus_decode_sc_chan.all;
use work.ipbus_reg_types.all;
......@@ -65,6 +62,8 @@ architecture rtl of sc_chan is
signal d_in, d_in_i, d_buf: std_logic_vector(13 downto 0);
signal d_c: std_logic_vector(1 downto 0);
signal slip, chan_rst, cap, inc: std_logic;
signal act_slip: unsigned(7 downto 0);
signal cntout: std_logic_vector(4 downto 0);
signal ctrl_en_sync, ctrl_en_buf, ctrl_invert: std_logic;
signal ctrl_mode: std_logic;
signal ctrl_src: std_logic_vector(1 downto 0);
......@@ -116,10 +115,23 @@ begin
ctrl_src <= ctrl(0)(7 downto 6);
slip <= sync_ctrl(0) and ctrl_en_sync; -- CDC
cap <= sync_ctrl(2) and ctrl_en_sync; -- CDC
inc <= sync_ctrl(3) and ctrl_en_sync; -- CDC
cap <= sync_ctrl(1) and ctrl_en_sync; -- CDC
inc <= sync_ctrl(2) and ctrl_en_sync; -- CDC
stat(0) <= X"000000" & "000" & err_i & dr_warn & dr_full & buf_full & cap_full; -- CDC
stat(0) <= X"00" & "000" & cntout & std_logic_vector(act_slip) & "000" & err_i & dr_warn & dr_full & buf_full & cap_full; -- CDC
-- Keep track of slips and taps for debug
process(clk40)
begin
if rising_edge(clk40) then
if rst40 = '1' then
act_slip <= X"00";
elsif slip = '1' then
act_slip <= act_slip + 1;
end if;
end if;
end process;
-- Input logic
......@@ -132,6 +144,7 @@ begin
d_n => d_n,
slip => slip,
inc => inc,
cntout => cntout,
q => d_in
);
......@@ -173,7 +186,7 @@ begin
qmask => (others => X"00003fff")
);
zs_sel_i <= to_integer(unsigned(zs_sel));
zs_sel_i <= to_integer(unsigned(zs_sel)); -- Might need pipelining here
zs_thresh <= zs_thresh_v(zs_sel_i)(13 downto 0) when zs_sel_i < N_ZS_THRESH else (others => '0');
-- Buffers
......
components/solid/firmware/hdl/sc_chan_buf.vhd
View file @ f98014ca
......@@ -2,6 +2,8 @@
--
-- The buffer chain for one input channel
--
-- Seriously, this stuff is mindfuck. If you are reading this, you are doomed.
--
-- Dave Newbold, May 2016
library IEEE;
......@@ -42,8 +44,8 @@ end sc_chan_buf;
architecture rtl of sc_chan_buf is
constant NZS_LAST_ADDR: integer := NZS_BLKS * 2 ** BLK_RADIX + ZS_DEL - 1;
constant ZS_FIRST_ADDR: integer := NZS_BLKS * 2 ** BLK_RADIX + ZS_DEL;
constant NZS_LAST_ADDR: integer := NZS_BLKS * 2 ** BLK_RADIX - 1;
constant ZS_FIRST_ADDR: integer := NZS_BLKS * 2 ** BLK_RADIX;
constant ZS_LAST_ADDR: integer := 2 ** BUF_RADIX - 1;
signal c: unsigned(1 downto 0);
......
components/solid/firmware/hdl/sc_daq.vhd
View file @ f98014ca
......@@ -33,6 +33,8 @@ entity sc_daq is
d_n: in std_logic_vector(N_CHAN - 1 downto 0);
clk125: in std_logic;
rst125: in std_logic;
pllclk: in std_logic;
pllrefclk: in std_logic;
board_id: in std_logic_vector(7 downto 0)
);
......@@ -212,9 +214,13 @@ begin
ipb_out => ipbr(N_SLV_TLINK),
clk125 => clk125,
rst125 => rst125,
pllclk => pllclk,
pllrefclk => pllrefclk,
link_ok => link_ok,
id => board_id,
clk40 => clk40_i,
rst40 => rst40_i,
sctr => sctr(15 downto 0),
d => link_d,
d_valid => link_d_valid,
q => link_q,
......
components/solid/firmware/hdl/sc_fake.vhd
View file @ f98014ca
......@@ -2,6 +2,9 @@
--
-- Fake data generator for trigger testing
--
-- mode = 0 is random data; mode = 1 is fake pulses
-- NB: for sample lock mode, pulse is issued 2 cycles after setting
--
-- Dave Newbold, June 2017
library IEEE;
......@@ -116,7 +119,7 @@ begin
end loop;
end process;
go <= '1' when ctrl_force = '1' or (or_reduce(mask and rand(27 downto 12)) = '0' and or_reduce(rand(11 downto 0)) = '0') else '0';
go <= '1' when ctrl_force = '1' or (ctrl_en = '1' and (or_reduce(mask and rand(27 downto 12)) = '0' and or_reduce(rand(11 downto 0)) = '0')) else '0';
samp <= '1' when ctrl_samp_lock = '0' or sctr = params_samp else '0';
pend <= (pend or (go and not act)) and not (rst40 or act) when rising_edge(clk40);
act <= (act or (pend and samp)) and not (rst40 or done) when rising_edge(clk40);
......
components/solid/firmware/hdl/sc_input_serdes.vhd
View file @ f98014ca
......@@ -19,6 +19,7 @@ entity sc_input_serdes is
d_n: in std_logic;
slip: in std_logic;
inc: in std_logic;
cntout: out std_logic_vector(4 downto 0);
q: out std_logic_vector(13 downto 0)
);
......@@ -55,7 +56,8 @@ begin
idatain => d_b,
datain => '0',
ldpipeen => '0',
dataout => d_d
dataout => d_d,
cntvalueout => cntout
);
clk_sb <= not clk_s;
......
components/solid/firmware/hdl/sc_local_trig.vhd
View file @ f98014ca
......@@ -20,6 +20,7 @@ entity sc_local_trig is
rst40: in std_logic;
en: in std_logic;
mask: in std_logic_vector(N_TRG - 1 downto 0);
hops: in std_logic_vector(31 downto 0);
mark: in std_logic;
sctr: in std_logic_vector(47 downto 0);
rand: in std_logic_vector(31 downto 0);
......@@ -74,7 +75,7 @@ begin
tg1: entity work.sc_trig_gen_or
generic map(
TBIT => 1,
DELAY => 3
DELAY => 4
)
port map(
clk => clk40,
......@@ -91,7 +92,7 @@ begin
tg2: entity work.sc_trig_gen_or
generic map(
TBIT => 2,
DELAY => 2
DELAY => 3
)
port map(
clk => clk40,
......@@ -136,7 +137,7 @@ begin
end loop;
end process;
trig_q <= X"00" & X"0" & std_logic_vector(to_unsigned(s, 4)); -- Hop count will go in 7:4 one day
trig_q <= X"00" & hops(s * 4 + 3 downto s * 4) & std_logic_vector(to_unsigned(s, 4));
trig_valid <= or_reduce(te) and not rveto;
process(s, trig_ack)
......
components/solid/firmware/hdl/sc_timing.vhd
View file @ f98014ca
......@@ -48,12 +48,15 @@ architecture rtl of sc_timing is
signal stat: ipb_reg_v(4 downto 0);
signal stb: std_logic_vector(0 downto 0);
signal sctr_i, sctr_s: unsigned(47 downto 0);
signal rst_ctr: unsigned(3 downto 0);
signal ctrl_rst_ctr, ctrl_cap_ctr, ctrl_en_sync, ctrl_force_sync, ctrl_pipeline_en, ctrl_send_sync: std_logic;
signal ctrl_chan_slip, ctrl_chan_rst_buf, ctrl_chan_cap, ctrl_chan_inc: std_logic;
signal frst, sync, sync_f, wait_sync, sync_err, io_err: std_logic;
signal ctrl_zs_blks: std_logic_vector(7 downto 0);
signal sync, wait_sync, sync_err, io_err: std_logic;
signal sync_in_r, trig_in_r, trig_in_r_d: std_logic;
signal sync_ctr, trig_ctr: unsigned(31 downto 0);
attribute IOB: string;
attribute IOB of sync_in_r, trig_in_r: signal is "TRUE";
begin
......@@ -104,10 +107,10 @@ begin
ctrl_pipeline_en <= ctrl(0)(5);
ctrl_send_sync <= ctrl(0)(6);
ctrl_chan_slip <= ctrl(0)(12);
ctrl_chan_rst_buf <= ctrl(0)(13);
ctrl_chan_cap <= ctrl(0)(14);
ctrl_chan_inc <= ctrl(0)(15);
stat(0) <= X"0000000" & '0' & io_err & sync_err & wait_sync;
ctrl_chan_cap <= ctrl(0)(13);
ctrl_chan_inc <= ctrl(0)(14);
ctrl_zs_blks <= ctrl(0)(23 downto 16);
stat(0) <= X"0000000" & "00" & sync_err & wait_sync;
stat(1) <= std_logic_vector(sctr_s(31 downto 0));
stat(2) <= X"0000" & std_logic_vector(sctr_s(47 downto 32));
stat(3) <= std_logic_vector(sync_ctr);
......@@ -139,7 +142,6 @@ begin
-- Sync signals
sync <= (sync_in_r and ctrl_en_sync) or (ctrl_force_sync and stb(0));
sync_f <= sync and wait_sync;
process(clk40_i)
begin
......@@ -158,7 +160,6 @@ begin
end if;
end process;
io_err <= '1';
led <= not (wait_sync or sync_err);
-- Sample counter
......@@ -166,7 +167,7 @@ begin
process(clk40_i)
begin
if rising_edge(clk40_i) then
if rst40_i = '1' or sync_f = '1' then
if rst40_i = '1' or wait_sync = '1' then
sctr_i <= X"000000000001";
else
sctr_i <= sctr_i + 1;
......@@ -195,7 +196,8 @@ begin
clk40 => clk40_i,
rst40 => rst40_i,
en => ctrl_pipeline_en,
sync => sync_f,
zs_blks => ctrl_zs_blks,
sync => sync,
sctr => sctr_i,
nzs_en => nzs_en,
zs_en => zs_en,
......@@ -203,23 +205,10 @@ begin
);
-- Channel sync control
process(clk40_i)
begin
if rising_edge(clk40_i) then
if rst40_i = '1' then
rst_ctr <= "0000";
elsif frst = '1' or (ctrl_chan_rst_buf = '1' and stb(0) = '1') then
rst_ctr <= rst_ctr + 1;
end if;
end if;
end process;
frst <= '1' when rst_ctr /= "1111" else '0';
chan_sync_ctrl(0) <= ctrl_chan_slip and stb(0); -- bitslip for serdes
chan_sync_ctrl(1) <= frst; -- reset channel
chan_sync_ctrl(2) <= ctrl_chan_cap and stb(0); -- cap start
chan_sync_ctrl(3) <= ctrl_chan_inc and stb(0); -- cap start
chan_sync_ctrl(1) <= ctrl_chan_cap and stb(0); -- cap start
chan_sync_ctrl(2) <= ctrl_chan_inc and stb(0); -- inc for idelay
chan_sync_ctrl(3) <= '0';
end rtl;
components/solid/firmware/hdl/sc_timing_startup.vhd
View file @ f98014ca
......@@ -16,6 +16,7 @@ entity sc_timing_startup is
clk40: in std_logic;
rst40: in std_logic;
en: in std_logic;
zs_blks: in std_logic_vector(7 downto 0);
sync: in std_logic;
sctr: in unsigned(47 downto 0);
nzs_en: out std_logic;
......@@ -45,11 +46,11 @@ begin
end if;
if up = '1' then
if and_reduce(std_logic_vector(sctr(BLK_RADIX - 1 downto 0))) = '1' then
if unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = 8 then
if unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = 0 then
nzs_en <= '1';
elsif unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = 8 + NZS_BLKS then
elsif unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = NZS_BLKS then
zs_en <= '1';
elsif unsigned(sctr(7 + BLK_RADIX downto BLK_RADIX)) = 7 + NZS_BLKS + ZS_BLKS then
elsif unsigned(sctr(7 + BLK_RADIX downto BLK_RADIX)) = NZS_BLKS - 1 + unsigned(zs_blks) then
trig_en <= '1';
end if;
end if;
......
components/solid/firmware/hdl/sc_trig.vhd
View file @ f98014ca
......@@ -59,6 +59,7 @@ architecture rtl of sc_trig is
signal ctrl_dtmon_en, ctrl_trig_in_en, ctrl_trig_out_force: std_logic;
signal masks: ipb_reg_v(N_CHAN_TRG * 2 - 1 downto 0);
signal trig_mask: std_logic_vector(N_TRG - 1 downto 0);
signal hop_cfg: std_logic_vector(31 downto 0);
signal ctrig: sc_trig_array;
signal lq: std_logic_vector(15 downto 0);
signal rveto, lvalid, lack, mark, err: std_logic;
......@@ -164,6 +165,18 @@ begin
);
trig_mask <= ctrl_mask(0)(N_TRG - 1 downto 0);
hop_reg: entity work.ipbus_reg_v
generic map(
N_REG => 1
)
port map(
clk => clk,
reset => rst,
ipbus_in => ipbw(N_SLV_HOP_CFG),
ipbus_out => ipbr(N_SLV_HOP_CFG),
q(0) => hop_cfg
);
ltrig: entity work.sc_local_trig
port map(
......@@ -171,6 +184,7 @@ begin
rst40 => rst40,
en => trig_en,
mask => trig_mask,
hops => hop_cfg,
mark => mark,
sctr => sctr,
rand => rand,
......@@ -189,7 +203,7 @@ begin
);
q <= lq;
q_valid <= lvalid;
q_valid <= lvalid when lq(7 downto 4) /= X"0" else '0';
-- ZS threshold select
......
components/solid/firmware/hdl/sc_trig_gen.vhd
View file @ f98014ca
......@@ -30,15 +30,15 @@ end sc_trig_gen;
architecture rtl of sc_trig_gen is
signal t, m, tc, v: std_logic;
signal mark_del: std_logic_vector(DELAY - 1 downto 0);
signal mark_del: std_logic_vector(DELAY downto 0);
begin
-- Define the trigger condition and block boundary
t <= trig;
mark_del <= mark_del(DELAY - 2 downto 0) & mark when rising_edge(clk);
m <= mark_del(DELAY - 1);
mark_del <= mark_del(DELAY - 1 downto 0) & mark when rising_edge(clk);
m <= mark_del(DELAY);
-- Catch a trigger feature with the block
......
components/solid/firmware/hdl/sc_trig_gen_or.vhd
View file @ f98014ca
......@@ -33,7 +33,7 @@ end sc_trig_gen_or;
architecture rtl of sc_trig_gen_or is
signal t, m, tc, v: std_logic;
signal mark_del: std_logic_vector(DELAY - 1 downto 0);
signal mark_del: std_logic_vector(DELAY downto 0);
signal c: std_logic_vector(N_CHAN - 1 downto 0);
begin
......@@ -41,8 +41,8 @@ begin
-- Define the trigger condition and block boundary
t <= or_reduce(chan_trig(TBIT));
mark_del <= mark_del(DELAY - 2 downto 0) & mark when rising_edge(clk);
m <= mark_del(DELAY - 1);
mark_del <= mark_del(DELAY - 1 downto 0) & mark when rising_edge(clk);
m <= mark_del(DELAY);
-- Catch a trigger feature with the block
......
components/solid/firmware/hdl/sc_trig_link.vhd
View file @ f98014ca
......@@ -8,6 +8,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
use work.ipbus_reg_types.all;
entity sc_trig_link is
port(
......@@ -17,9 +18,13 @@ entity sc_trig_link is
ipb_out: out ipb_rbus;
clk125: in std_logic;
rst125: in std_logic;
pllclk: in std_logic;
pllrefclk: in std_logic;
link_ok: out std_logic;
id: in std_logic_vector(7 downto 0);
clk40: in std_logic;
rst40: in std_logic;
sctr: in std_logic_vector(15 downto 0);
d: in std_logic_vector(15 downto 0);
d_valid: in std_logic;
q: out std_logic_vector(15 downto 0);
......@@ -31,11 +36,148 @@ end sc_trig_link;
architecture rtl of sc_trig_link is
signal ctrl: ipb_reg_v(0 downto 0);
signal stat: ipb_reg_v(1 downto 0);
signal ctrl_en_us, ctrl_en_ds, ctrl_rst_tx, ctrl_rst_rx: std_logic;
signal ctrl_loopback_us, ctrl_loopback_ds: std_logic_vector(2 downto 0);
signal rdy_us_tx, rdy_us_rx, rdy_ds_tx, rdy_ds_rx: std_logic;
signal stat_us_tx, stat_ds_tx: std_logic_vector(1 downto 0);
signal stat_us_rx, stat_ds_rx: std_logic_vector(2 downto 0);
signal txd_us, rxd_us, txd_ds, rxd_ds: std_logic_vector(15 downto 0);
signal txk_us, rxk_us, txk_ds, rxk_ds: std_logic_vector(1 downto 0);
signal id_us, id_ds: std_logic_vector(7 downto 0);
signal qv_us, qv_ds, ack_us, ack_ds, data_good_us, data_good_ds: std_logic;
signal q_us, q_ds: std_logic_vector(15 downto 0);
signal pstat_us_tx, pstat_ds_tx: std_logic_vector(1 downto 0);
signal pstat_us_rx, pstat_ds_rx: std_logic_vector(4 downto 0);
begin
ipb_out <= IPB_RBUS_NULL;
q <= (others => '0');
q_valid <= '0';
link_ok <= '0';
-- CSR
csr: entity work.ipbus_ctrlreg_v
generic map(
N_CTRL => 1,
N_STAT => 2
)
port map(
clk => clk,
reset => rst,
ipbus_in => ipb_in,
ipbus_out => ipb_out,
d => stat,
q => ctrl
);
ctrl_en_us <= ctrl(0)(0);
ctrl_en_ds <= ctrl(0)(1);
ctrl_rst_tx <= ctrl(0)(2);
ctrl_rst_rx <= ctrl(0)(3);
ctrl_loopback_us <= ctrl(0)(6 downto 4);
ctrl_loopback_ds <= ctrl(0)(9 downto 7);
stat(0) <= X"00" & id_us & '0' & pstat_us_rx & pstat_us_tx & '0' & stat_us_rx & stat_us_tx & rdy_us_rx & rdy_us_tx;
stat(1) <= X"00" & id_ds & '0' & pstat_ds_rx & pstat_ds_tx & '0' & stat_ds_rx & stat_ds_tx & rdy_ds_rx & rdy_ds_tx;
-- MGTs
mgt_us: entity work.sc_trig_mgt_wrapper
port map(
sysclk => clk,
en => ctrl_en_us,
tx_rst => ctrl_rst_tx,
rx_rst => ctrl_rst_rx,
tx_good => rdy_us_tx,
rx_good => rdy_us_rx,
tx_stat => stat_us_tx,
rx_stat => stat_us_rx,
pllclk => pllclk,
pllrefclk => pllrefclk,
loopback => ctrl_loopback_us,
clk125 => clk125,
txd => txd_us,
txk => txk_us,
rxd => rxd_us,
rxk => rxk_us
);
mgt_ds: entity work.sc_trig_mgt_wrapper
port map(
sysclk => clk,
en => ctrl_en_ds,
tx_rst => ctrl_rst_tx,
rx_rst => ctrl_rst_rx,
tx_good => rdy_ds_tx,
rx_good => rdy_ds_rx,
tx_stat => stat_ds_tx,
rx_stat => stat_ds_rx,
pllclk => pllclk,
pllrefclk => pllrefclk,
loopback => ctrl_loopback_ds,
clk125 => clk125,
txd => txd_ds,
txk => txk_ds,
rxd => rxd_ds,
rxk => rxk_ds
);
-- Data pipeline
pipe_from_us: entity work.sc_trig_link_pipe
port map(
en => ctrl_en_us,
clk125 => clk125,
rxd => rxd_us,
rxk => rxk_us,
link_good => rdy_us_rx,
txd => txd_ds,
txk => txk_ds,
clk40 => clk40,
rst40 => rst40,
sctr => sctr,
d => d,
dv => d_valid,
q => q_us,
qv => qv_us,
ack => ack_us,
stat_rx => pstat_us_rx,
stat_tx => pstat_us_tx,
my_id => id,
remote_id => id_us,
data_good => data_good_us
);
pipe_from_ds: entity work.sc_trig_link_pipe
port map(
en => ctrl_en_ds,
clk125 => clk125,
rxd => rxd_ds,
rxk => rxk_ds,
link_good => rdy_ds_rx,
txd => txd_us,
txk => txk_us,
clk40 => clk40,
rst40 => rst40,
sctr => sctr,
d => d,
dv => d_valid,
q => q_ds,
qv => qv_ds,
ack => ack_ds,
stat_rx => pstat_ds_rx,
stat_tx => pstat_ds_tx,
my_id => id,
remote_id => id_ds,
data_good => data_good_ds
);
-- Merger
q <= q_us when qv_us = '1' else q_ds;
q_valid <= qv_us or qv_ds;
ack_us <= ack and qv_us;
ack_ds <= ack and not qv_us;
link_ok <= ((rdy_us_tx and rdy_us_rx and data_good_us) or not ctrl_en_us) and
((rdy_ds_tx and rdy_ds_rx and data_good_ds) or not ctrl_en_ds);
end rtl;
components/solid/firmware/hdl/sc_trig_link_pipe.vhd 0 → 100644
View file @ f98014ca
-- sc_trig_link_pipe
--
-- Data path logic for trigger links
--
-- Dave Newbold, October 2017
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.VComponents.all;
entity sc_trig_link_pipe is
port(
en: in std_logic;
clk125: in std_logic;
rxd: in std_logic_vector(15 downto 0);
rxk: in std_logic_vector(1 downto 0);
link_good: in std_logic;
txd: out std_logic_vector(15 downto 0);
txk: out std_logic_vector(1 downto 0);
clk40: in std_logic;
rst40: in std_logic;
sctr: in std_logic_vector(15 downto 0);
d: in std_logic_vector(15 downto 0);
dv: in std_logic;
q: out std_logic_vector(15 downto 0);
qv: out std_logic;
ack: in std_logic;
stat_rx: out std_logic_vector(4 downto 0);
stat_tx: out std_logic_vector(1 downto 0);
my_id: in std_logic_vector(7 downto 0);
remote_id: out std_logic_vector(7 downto 0);
data_good: out std_logic
);
end sc_trig_link_pipe;
architecture rtl of sc_trig_link_pipe is
signal rx_valid: std_logic;
signal di_rx, do_rx, di_tx, do_tx: std_logic_vector(31 downto 0);
signal v, ren_rx, ren_tx, wen_tx, empty_rx, full_rx, empty_tx, full_tx: std_logic;
signal f: std_logic_vector(15 downto 0);
signal up, fail, cause, tb: std_logic;
signal cctr: unsigned(8 downto 0);
begin
-- Input FIFO
rx_valid <= '1' when rxk = "00" and link_good = '1' else '0';
di_rx <= X"0000" & rxd;
rx_fifo: FIFO18E1
generic map(
DATA_WIDTH => 18,
FIRST_WORD_FALL_THROUGH => true
)
port map(
di => di_rx,
dip => "0000",
do => do_rx,
empty => empty_rx,
full => full_rx,
rdclk => clk40,
rden => ren_rx,
regce => '1',
rst => rst40,
rstreg => '0',
wrclk => clk125,
wren => rx_valid
);
q <= do_rx(15 downto 0);
qv <= up and not empty_rx;
stat_rx(1 downto 0) <= full_rx & empty_rx;
ren_rx <= (ack or tb or not up) and en;
-- Data checker: rx
tb <= '1' when do_rx(3 downto 0) = X"f" and empty_rx = '0' else '0';
process(clk40)
begin
if rising_edge(clk40) then
if rst40 = '1' or en = '0' or link_good = '0' then -- CDC, en is on clk_ipb, but ~static level
up <= '0';
fail <= '0';
cause <= '0';
elsif tb = '1' then
if up = '0' then
if fail = '0' and do_rx(15 downto 8) = sctr(15 downto 8) then
up <= '1';
cctr <= (others => '0');
end if;
else
if do_rx(15 downto 8) /= sctr(15 downto 8) then
up <= '0';
fail <= '1';
else
cctr <= (others => '0');
end if;
end if;
elsif up = '1' then
if and_reduce(std_logic_vector(cctr)) = '1' then -- Timeout between block markers
up <= '0';
fail <= '1';
cause <= '1';
else
cctr <= cctr + 1;
end if;
end if;
end if;
end process;
data_good <= up;
stat_rx(2) <= up;
stat_rx(3) <= fail;
stat_rx(4) <= cause;
-- Trigger forwarding and hop count
process(clk125)
begin
if rising_edge(clk125) then
f <= rxd(15 downto 8) & std_logic_vector(unsigned(rxd(7 downto 4)) - 1) & rxd(3 downto 0);
if rx_valid = '1' and rxd(7 downto 4) /= "0001" and up = '1' then
v <= '1';
else
v <= '0';
end if;
end if;
end process;
-- Output FIFO
di_tx <= X"0000" & d when or_reduce(sctr(7 downto 0)) = '1' else X"0000" & sctr(15 downto 8) & X"1f";
tx_fifo: FIFO18E1
generic map(
DATA_WIDTH => 18,
FIRST_WORD_FALL_THROUGH => true
)
port map(
di => di_tx,
dip => "0000",
do => do_tx,
empty => empty_tx,
full => full_tx,
rdclk => clk125,
rden => ren_tx,
regce => '1',
rst => rst40,
rstreg => '0',
wrclk => clk40,
wren => wen_tx
);
stat_tx <= full_tx & empty_tx;
ren_tx <= not empty_tx and not v;
wen_tx <= dv or not or_reduce(sctr(7 downto 0));
-- Link output select
process(f, do_tx, my_id, v, empty_tx)
begin
if v = '1' then
txd <= f;
txk <= "00";
elsif empty_tx = '0' then
txd <= do_tx(15 downto 0);
txk <= "00";
else
txd <= X"bc" & my_id;
txk <= "10";
end if;
end process;
-- Remote link ID
remote_id <= rxd(7 downto 0) when rising_edge(clk125) and rxk = "10" and link_good = '1';
end rtl;
components/solid/firmware/hdl/sc_trig_mgt_wrapper.vhd 0 → 100644
View file @ f98014ca
This diff is collapsed.
components/solid/firmware/hdl/sc_trig_ro_block.vhd
View file @ f98014ca
......@@ -34,7 +34,6 @@ end sc_trig_ro_block;
architecture rtl of sc_trig_ro_block is
constant OFFSET: integer := (NZS_BLKS + ZS_BLKS) * 2 ** BLK_RADIX;
signal tctr_i: unsigned(27 downto 0);
signal go, blkend: std_logic;
signal chen, keep_c: std_logic_vector(63 downto 0);
......@@ -68,7 +67,7 @@ begin
with ro_ctr select ro_q <=
X"0" & std_logic_vector(tctr_i) when X"00", -- Type 0
std_logic_vector(unsigned(sctr(31 downto 1) & '0') - OFFSET) when X"01", -- Hack so that counter is taken at start-of-block
std_logic_vector(unsigned(sctr(31 downto 1) & '0')) when X"01", -- Hack so that counter is taken at start-of-block
X"0000" & std_logic_vector(sctr(47 downto 32)) when X"02",
chen(31 downto 0) when X"03", -- Corresponds to CH_WORD = 3 in sc_roc
chen(63 downto 32) when X"04",
......
components/solid/firmware/hdl/sc_zs_sel.vhd
View file @ f98014ca
......@@ -25,35 +25,23 @@ end sc_zs_sel;
architecture rtl of sc_zs_sel is
signal mark_del: std_logic_vector(ZS_DEL - 1 downto 0);
signal m, g: std_logic;
signal t: unsigned(3 downto 0);
signal sel_i: std_logic_vector(1 downto 0);
signal ti: integer range 15 downto 0 := 0;
signal zs: std_logic_vector(1 downto 0);
begin
mark_del <= mark_del(ZS_DEL - 2 downto 0) & mark when rising_edge(clk40);
m <= mark_del(ZS_DEL - 1);
ti <= to_integer(unsigned(trig(3 downto 0)));
zs <= zscfg(ti * 2 + 1 downto ti * 2);
process(clk40)
begin
if rising_edge(clk40) then
if rst40 = '1' or m = '1' then
t <= (others => '0');
g <= '0';
elsif trig_valid = '1' then
g <= '1';
if unsigned(trig(3 downto 0)) > t then
t <= unsigned(trig(3 downto 0));
end if;
end if;
if rst40 = '1' then
sel <= "00";
elsif m = '1' then
if g = '0' then
sel <= "00";
else
sel <= zscfg(to_integer(t) * 2 + 1 downto to_integer(t) * 2);
end if;
if rst40 = '1' or mark = '1' then
sel_i <= "00";
sel <= sel_i;
elsif trig_valid = '1' and unsigned(zs) > unsigned(sel_i) then
sel_i <= zs;
end if;
end if;
end process;
......
components/solid/firmware/sim_hdl/sc_trig_mgt_sim.vhd 0 → 100644
View file @ f98014ca
-- sc_trig_mgt_sim
--
-- Wrapper for GTP blocks; dummy version for sim
--
-- Dave Newbold, October 2017
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sc_trig_mgt_wrapper is
port(
sysclk: in std_logic; -- DRP clock
en: in std_logic;
tx_rst: in std_logic;
rx_rst: in std_logic;
tx_good: out std_logic;
rx_good: out std_logic;
tx_stat: out std_logic_vector(1 downto 0);
rx_stat: out std_logic_vector(2 downto 0);
pllclk: in std_logic;
pllrefclk: in std_logic;
loopback: in std_logic_vector(2 downto 0);
clk125: in std_logic;
txd: in std_logic_vector(15 downto 0);
txk: in std_logic_vector(1 downto 0);
rxd: out std_logic_vector(15 downto 0);
rxk: out std_logic_vector(1 downto 0)
);
end sc_trig_mgt_wrapper;
architecture rtl of sc_trig_mgt_wrapper is
begin
tx_good <= en;
rx_good <= en;
tx_stat <= "00";
rx_stat <= "000";
rxd <= txd when rising_edge(clk125);
rxk <= txk when rising_edge(clk125);
end rtl;
projects/64ch/firmware/hdl/payload.vhd
View file @ f98014ca
......@@ -24,6 +24,8 @@ entity payload is
clk125: in std_logic;
rst125: in std_logic;
clk200: in std_logic;
pllclk: in std_logic;
pllrefclk: in std_logic;
nuke: out std_logic;
soft_rst: out std_logic;
stealth_mode: out std_logic;
......@@ -157,10 +159,12 @@ begin
led_out => daq_led,
chan => ctrl_chan,
chan_err => chan_err,
d_p => adc_d_p,
d_n => adc_d_n,
d_p => adc_d_p(N_CHAN - 1 downto 0),
d_n => adc_d_n(N_CHAN - 1 downto 0),
clk125 => clk125,
rst125 => rst125,
pllclk => pllclk,
pllrefclk => pllrefclk,
board_id => addr
);
......
projects/64ch/firmware/hdl/top_decl.vhd
View file @ f98014ca
......@@ -11,15 +11,12 @@ package top_decl is
constant MAC_ADDR: std_logic_vector(47 downto 0) := X"020ddba11500"; -- last byte from local addr
constant IP_ADDR: std_logic_vector(31 downto 0) := X"c0a8eb00"; -- last byte from local addr
constant FW_REV: std_logic_vector(15 downto 0) := X"0010";
constant FW_REV: std_logic_vector(15 downto 0) := X"0011";
constant N_CHAN: integer := 64;
constant BLK_RADIX: integer := 8; -- 256 sample blocks
constant SUPERBLK_RADIX: integer := 16; -- Superblock is 64k blocks
constant BUF_RADIX: integer := 11; -- One BRAM for NZS / ZS buffer
constant NZS_BLKS: integer := 2; -- Reserve two blocks of space for NZS buffer
constant ZS_BLKS: integer := 2; -- Time window for ZS buffer
constant ZS_DEL: integer := 8; -- Additional samples to form channel trigger
constant N_TRG: integer := 4; -- Number of trigger types
constant N_ZS_THRESH: integer := 4; -- Number of ZS thresholds
constant N_CHAN_TRG: integer := 3; -- Number of channel trigger bits
......
projects/64ch/software/Si5345_status.py
View file @ f98014ca
......@@ -7,7 +7,8 @@ from I2CuHal import I2CCore
from si5344 import si5344
uhal.setLogLevelTo(uhal.LogLevel.ERROR)
hw = uhal.getDevice("board", "ipbusudp-2.0://192.168.235.55:50001", "file://addrtab/top.xml")
manager = uhal.ConnectionManager("file://connections.xml")
hw = manager.getDevice(sys.argv[1])
hw.getNode("csr.ctrl.soft_rst").write(1) # Reset ipbus registers
hw.dispatch()
......
projects/64ch/software/align_adc.py 100644 → 100755
View file @ f98014ca
......@@ -37,6 +37,9 @@ invert = [0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25]
uhal.setLogLevelTo(uhal.LogLevel.ERROR)
board = uhal.getDevice("board", "ipbusudp-2.0://192.168.235.50:50001", "file://addrtab/top.xml")
#board = uhal.getDevice("board", "ipbusudp-2.0://192.168.235.16:50001", "file://addrtab/top_sim.xml")
#uhal.setLogLevelTo(uhal.LogLevel.INFO)
#manager = uhal.ConnectionManager("file://connections.xml")
#board = manager.getDevice(sys.argv[1])
board.getClient().setTimeoutPeriod(10000)
v = board.getNode("csr.id").read()
......@@ -50,7 +53,7 @@ board.dispatch()
time.sleep(1)
chans = range(0x40)
chans = range(0x1)
adcs = range(0x10)
patt = 0x0ff
cap_len = 0x80
......@@ -83,6 +86,13 @@ for i_chan in chans:
for i_slip in range(14):
ok = False
for i_tap in range(32):
atap = board.getNode("daq.chan.csr.stat.tap").read()
aslip = board.getNode("daq.chan.csr.stat.slip").read()
board.dispatch()
print "Set slip, tap ; actual slip, tap", hex(i_slip), hex(i_tap), hex(aslip), hex(atap)
if i_slip != aslip or i_tap != atap:
print "Colossal bullshit has occured"
sys.exit()
board.getNode("daq.timing.csr.ctrl.chan_cap").write(0x1) # Capture
board.getNode("daq.timing.csr.ctrl.chan_cap").write(0x0)
board.dispatch()
......
projects/64ch/software/align_adc_bulk.py
View file @ f98014ca
......@@ -8,34 +8,37 @@ import collections
sys.path.append('/home/dsaunder/workspace/go_projects/src/bitbucket.org/solidexperiment/readout-software/scripts/')
import detector_config_tools
def spi_config(spi, div, ctrl, ss):
spi.getNode("divider").write(0xf) # Divide 31.25MHz ipbus clock by 32
spi.getNode("ctrl").write(0x2410) # 16b transfer length, auto CSN
spi.getNode("ss").write(0x1) # Enable SPI slave 0
spi.getClient().dispatch()
spi.getNode("divider").write(0xf) # Divide 31.25MHz ipbus clock by 32
spi.getNode("ctrl").write(0x2410) # 16b transfer length, auto CSN
spi.getNode("ss").write(0x1) # Enable SPI slave 0
spi.getClient().dispatch()
def spi_write(spi, addr, data):
spi.getNode("d0").write((addr << 8) + data) # Write data into addr
spi.getNode("ctrl").write(0x2510) # Do it
spi.getClient().dispatch()
r = spi.getNode("ctrl").read()
spi.getClient().dispatch()
if r & 0x100 != 0:
print "SPI write error", hex(addr), hex(data)
spi.getNode("d0").write((addr << 8) + data) # Write data into addr
spi.getNode("ctrl").write(0x2510) # Do it
spi.getClient().dispatch()
r = spi.getNode("ctrl").read()
spi.getClient().dispatch()
if r & 0x100 != 0:
print "SPI write error", hex(addr), hex(data)
def spi_read(spi, addr):
spi.getNode("d0").write(0x8000 + (addr << 8)) # Read from addr
spi.getNode("ctrl").write(0x2510) # Do it
spi.getClient().dispatch()
d = spi.getNode("d0").read()
r = spi.getNode("ctrl").read()
spi.getClient().dispatch()
if r & 0x100 != 0:
print "SPI read error", hex(addr)
return d & 0xffff
spi.getNode("d0").write(0x8000 + (addr << 8)) # Read from addr
spi.getNode("ctrl").write(0x2510) # Do it
spi.getClient().dispatch()
d = spi.getNode("d0").read()
r = spi.getNode("ctrl").read()
spi.getClient().dispatch()
if r & 0x100 != 0:
print "SPI read error", hex(addr)
return d & 0xffff
offsets = [0, 13, 2, 1, 4, 3, 6, 5, 8, 7, 10, 9, 12, 11]
invert = [0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25]
uhal.setLogLevelTo(uhal.LogLevel.ERROR)
# Db stuff.
ips = detector_config_tools.currentIPs(False)
db = dataset.connect('mysql://DAQGopher:gogogadgetdatabase@localhost/solid_phase1_running')
......@@ -49,9 +52,10 @@ iBoard = -1
for ith_ip in ips:
iBoard += 1
ith_slips, ith_taps = [], []
print '\n\n*********** About to align ip:', ith_ip
print '\nAbout to align ip:', ith_ip
board = uhal.getDevice("board", "ipbusudp-2.0://192.168.235." + str(ith_ip) + ":50001", "file://addrtab/top.xml")
board.getClient().setTimeoutPeriod(10000)
v = board.getNode("csr.id").read()
board.dispatch()
......@@ -63,7 +67,7 @@ for ith_ip in ips:
time.sleep(1)
chans = range(0x40)
chans = range(0x1)
adcs = range(0x10)
patt = 0x0ff
cap_len = 0x80
......@@ -93,7 +97,7 @@ for ith_ip in ips:
res = [False] * (17 * taps_per_slip)
tr = []
for i_slip in range(14):
for i_slip in range(1):
ok = False
for i_tap in range(32):
board.getNode("daq.timing.csr.ctrl.chan_cap").write(0x1) # Capture
......@@ -102,13 +106,12 @@ for ith_ip in ips:
time.sleep(0.01)
while True:
r = board.getNode("daq.chan.csr.stat").read()
board.getNode("daq.chan.buf.addr").write(0x0)
d = board.getNode("daq.chan.buf.data").readBlock(cap_len)
board.dispatch()
if r & 0x1 == 1:
break
print "Crap no capture", hex(i_chan), hex(i_slip), hex(i_tap), hex(r), time.clock()
c = 0
<<<<<<< HEAD
for w in d:
if int(w) & 0x3ff == patt:
c += 1
......@@ -118,6 +121,9 @@ for ith_ip in ips:
res[l] = (c == cap_len)
#res[i_slip * taps_per_slip + i_tap] = (c == cap_len)
if c==cap_len: workers.append([i_slip, i_tap])
=======
res[offsets[i_slip] * taps_per_slip + (31 - i_tap)] = (c == cap_len)
>>>>>>> a1628f5b1f63ca4804f5919005d9e7f3db8ac00c
ok = (c == cap_len) or ok
board.getNode("daq.timing.csr.ctrl.chan_inc").write(0x1) # Increment tap
board.getNode("daq.timing.csr.ctrl.chan_inc").write(0x0)
......@@ -150,6 +156,7 @@ for ith_ip in ips:
trp += "+"
else:
trp += "."
<<<<<<< HEAD
a = int((min + max) / 2)
l_tap = taps_per_slip
d_slip = 0
......@@ -169,6 +176,15 @@ for ith_ip in ips:
#ith_slips.append(workers[len(workers)/2][0])
#ith_taps.append(workers[len(workers)/2][1])
print trp
=======
a = int((min + max) / 2)
d_slip = offsets.index(a // taps_per_slip)
d_tap = a % taps_per_slip
print trp
db['TapSlips'].insert({'configID': int(configID), 'ip': ith_ip, 'tap': d_tap, 'slip': d_slip, 'channel': i_chan})
ith_slips.append(d_slip)
ith_taps.append(d_tap)
>>>>>>> a1628f5b1f63ca4804f5919005d9e7f3db8ac00c
if not non_cont:
print "Chan, rec_slip, rec_tap:", i_chan, d_slip, d_tap, '\t', iBoard
else:
......
projects/64ch/software/check_sync.py
View file @ f98014ca
......@@ -12,6 +12,9 @@ import detector_config_tools
uhal.setLogLevelTo(uhal.LogLevel.ERROR)
ips = detector_config_tools.currentIPs(False)
#ips = [58]
#manager = uhal.ConnectionManager("file://connections.xml")
#hw = manager.getDevice(sys.argv[1])
while True:
print '\n', time.ctime(),
for ip in ips:
......
projects/64ch/software/connections.xml 0 → 100644
View file @ f98014ca
<?xml version="1.0" encoding="UTF-8"?>
<connections>
<connection id="MAROC_64CH" uri="ipbusudp-2.0://192.168.235.50:50001"
address_table="file://addrtab/top.xml" />
<connection id="SIM" uri="ipbusudp-2.0://192.168.235.16:50001"
address_table="file://addrtab/top_sim.xml" />
<connection id="BEK_8CH" uri="ipbusudp-2.0://192.168.235.1:50001"
address_table="file://addrtab/top_sim.xml" />
</connections>
projects/64ch/software/ro_test.py
View file @ f98014ca
......@@ -6,7 +6,7 @@ import sys
import collections
def zsdot(i):
return ' ' if i == 0 else '!'
return ' ' if i == 0 else '*'
def zsfmt(i):
return "%s%s%04x %s%s%04x" % (zsdot(i & 0x8000), zsdot(i & 0x4000), i & 0x3fff,
......@@ -25,13 +25,13 @@ def dump():
print "Evt_ctr: %08x Trig_stat: %08x Roc_stat: %08x Buf_cnt: %08x Roc_tot: %08x Chan_stat: %08x Wctr: %08x" % (int(b0), int(b1), int(b2), int(b3), int(b4), int(b5), int(b6))
uhal.setLogLevelTo(uhal.LogLevel.ERROR)
board = uhal.getDevice("board", "ipbusudp-2.0://192.168.235.50:50001", "file://addrtab/top.xml")
#board = uhal.getDevice("board", "ipbusudp-2.0://192.168.235.16:50001", "file://addrtab/top_sim.xml")
manager = uhal.ConnectionManager("file://connections.xml")
board = manager.getDevice(sys.argv[1])
board.getClient().setTimeoutPeriod(10000)
v = board.getNode("csr.id").read()
board.dispatch()
print hex(v)
print "Board ID:", hex(v)
board.getNode("daq.timing.csr.ctrl.rst").write(1) # Hold clk40 domain in reset
board.dispatch()
......@@ -41,31 +41,54 @@ board.dispatch()
sleep(1)
for i in range(8):
for i in range(1):
board.getNode("csr.ctrl.chan").write(i) # Talk to channel 0
board.getNode("daq.chan.csr.ctrl.mode").write(0x0) # Set to normal DAQ mode
board.getNode("daq.chan.csr.ctrl.src").write(0x0) # Set source to random number generator
board.getNode("daq.chan.csr.ctrl.zs_thresh").write(0x3fff) # Set ZS threshold
board.getNode("daq.chan.csr.ctrl.src").write(0x3) # Set source to fake data
board.getNode("daq.chan.zs_thresh").writeBlock([0x0, 0x1]) # Set ZS thresholds #0 = 0, #1 =1
board.getNode("daq.chan.trig_thresh.threshold.thresh").write(0x1000) # Set ctrig 0 threshold
board.getNode("daq.chan.csr.ctrl.en_buf").write(0x1) # Enable this channel
board.getNode("daq.rtrig.ctrl.dist").write(0x1) # Set random trigger generator to interval mode
board.getNode("daq.rtrig.ctrl.div").write(0xa) # Set random trigger rate to 40MHz / 2^11 = 20kHz
board.getNode("daq.rtrig.ctrl.en").write(0x1) # Enable random trigger generator
board.getNode("daq.trig.loc_mask").write(0x8) # Enable trigger type 3 (random trigger)
board.getNode("daq.trig.seq.conf.addr").write(0x3) # Set sequencer table to entry 0 (trigger type 0)
board.getNode("daq.trig.seq.conf.data").write(0x00010000) # Set offet = 0, block count = 1 for trigger type 0
board.getNode("daq.fake.ctrl.mode").write(0x1) # Set fake data to pulse
board.getNode("daq.fake.ctrl.samp_lock").write(0x1) # Lock to sample
board.getNode("daq.fake.params.freq.freq_div").write(0x0) # Fake pulse once per 4096 samples
board.getNode("daq.fake.params.freq.samp").write(0xfd) # pulse on sample 0
board.getNode("daq.fake.params.freq.n").write(0x1) # One ping only
board.getNode("daq.fake.params.size.level").write(0x2000) # Pulse height
board.getNode("daq.fake.params.size.ped").write(0x0) # Pedestal
#board.getNode("daq.rtrig.ctrl.dist").write(0x1) # Set random trigger generator to interval mode
#board.getNode("daq.rtrig.ctrl.div").write(0x3) # Set random trigger rate to 40MHz / 2^11 = 20kHz
#board.getNode("daq.rtrig.ctrl.en").write(0x1) # Enable random trigger generator
#board.getNode("daq.trig.loc_mask").write(0x8) # Enable trigger type 3 (random trigger)
#board.getNode("daq.trig.seq.conf.addr").write(0x3) # Set sequencer table pointer to entry 3 (trigger type 3)
#board.getNode("daq.trig.seq.conf.data").write(0x00010000) # Set offset = 0, block count = 1
board.getNode("daq.trig.masks").write(0x1) # Enable ctrig bit 0 for channel 0
board.getNode("daq.trig.loc_mask").write(0x1) # Enable trigger type 0 (threshold trigger)
board.getNode("daq.trig.seq.conf.addr").write(0x0) # Set sequencer table pointer to entry 0
board.getNode("daq.trig.seq.conf.data").write(0x00040000) # Set offset = 0, block count = 4
board.getNode("daq.trig.zs_cfg").write(0x01) # Set zs thresh #1 for trigger 0
board.getNode("daq.roc.csr.ctrl.en").write(0x1) # Enable readout buffer
board.getNode("daq.timing.csr.ctrl.zs_blks").write(0x2) # Configure buffers for two ZS blocks
board.getNode("daq.timing.csr.ctrl.pipeline_en").write(1) # Enable front-end pipeline
board.getNode("daq.timing.csr.ctrl.force_sync").write(1) # And... go.
board.dispatch()
print "Started DAQ"
sleep(1)
r = list()
evts = 0
max_evts = 8
max_evts = 16
n_trig = 4
print "Firing triggers"
for i in range(1):
board.getNode("daq.fake.ctrl.force").write(0x1)
board.getNode("daq.fake.ctrl.force").write(0x0)
board.dispatch()
while True:
while True:
......@@ -74,8 +97,6 @@ while True:
if v1 != 0:
break
# dump()
b = board.getNode("daq.roc.buf.data").readBlock(int(v1)) # Read the buffer contents
board.dispatch()
......@@ -83,7 +104,7 @@ while True:
while len(r) > 0:
m = int(r.pop(0))
m = int(r[0])
if (m >> 24) != 0xaa:
print "Bad news: event header incorrect"
dump()
......@@ -93,21 +114,22 @@ while True:
sys.exit()
l = m & 0xffff
if len(r) >= l:
w0 = int(r.pop(0))
print hex(w0)
rtype = (w0 >> 28)
print "Readout type %d Len %04x" % (rtype, l)
w0 = int(r.pop(0))
w1 = int(r.pop(0))
rtype = (w1 >> 28)
print "Shop! w0: %08x w1: %08x ro_type: %d len: %04x" % (w0, w1, rtype, l)
if rtype == 0: # A data block
bctr = w0 & 0xffffff
bctr = w1 & 0xffffff
tstamp = int(r.pop(0)) | (int(r.pop(0)) << 32)
mask = int(r.pop(0)) | int(r.pop(0)) >> 32
for _ in range(2):
r.pop(0)
c = bin(mask).count('1')
print "\tBlock %08x Time %012x Mask %016x Chans %02x" % (bctr, tstamp, mask, c)
print "\tctr: %08x time: %012x mask: %016x chans: %02x" % (bctr, tstamp, mask, c)
tcnt = 0
for i in range(c):
print "%04x" % 0,
print "\tchan %02x" % (i)
print "\t\t%04x" % 0,
cnt = 0
zcnt = 0
while True:
......@@ -124,11 +146,11 @@ while True:
zcnt += ((g & 0x3fff0000) >> 16)
print zsfmt(g),
if cnt % 8 == 0:
print "\n%04x" % cnt,
print "\n\t\t%04x" % cnt,
if g & 0x80008000 != 0:
print
break;
print "\t\tChan %02x" % i, "Len: %04x" % cnt, "Zlen: %04x" % zcnt
print "\t\tlen: %04x" % cnt, "zlen: %04x" % zcnt
if zcnt != 0x100:
print "Bad news: chan %02x zcnt is %04x" % (i, zcnt)
dump()
......@@ -140,11 +162,12 @@ while True:
if evts >= max_evts:
sys.exit()
elif rtype == 1: # A trigger block
ttype = w0 & 0x3ffff
ttype = w1 & 0x3ffff
tstamp = int(r.pop(0)) | (int(r.pop(0)) << 32)
for _ in range(2 * n_trig + 1):
print hex(r.pop(0))
print "\tTbits %08x Time %012x" % (ttype, tstamp)
# print hex(r.pop(0))
r.pop(0)
print "\ttbits: %08x time: %012x" % (ttype, tstamp)
else:
print "Unknown readout type"
sys.exit()
......
projects/64ch/software/setup.py
View file @ f98014ca
......@@ -40,6 +40,33 @@ for ip in ips:
f_lock = hw.getNode("csr.stat.mmcm_locked").read();
hw.dispatch()
print "csr.stat.mmcm_lock", hex(f_lock)
=======
uhal.setLogLevelTo(uhal.LogLevel.INFO)
manager = uhal.ConnectionManager("file://connections.xml")
hw = manager.getDevice(sys.argv[1])
hw.getNode("csr.ctrl.soft_rst").write(1) # Reset ipbus registers
hw.dispatch()
hw.getNode("csr.ctrl.io_sel").write(9) # Talk via CPLD to Si5345
clock_I2C = I2CCore(hw, 10, 5, "io.i2c", None)
zeClock=si5344(clock_I2C)
res= zeClock.getDeviceVersion()
#regCfgList=zeClock.parse_clk("Si5345-RevD-SOL64CZW-SOL64CHW-Registers.txt")
regCfgList=zeClock.parse_clk("Si5345-internal.txt")
zeClock.writeConfiguration(regCfgList)
hw.getNode("io.freq_ctr.ctrl.chan_sel").write(0);
hw.getNode("io.freq_ctr.ctrl.en_crap_mode").write(0);
hw.dispatch()
time.sleep(2)
fq = hw.getNode("io.freq_ctr.freq.count").read();
fv = hw.getNode("io.freq_ctr.freq.valid").read();
hw.dispatch()
print "Freq:", int(fv), int(fq) * 119.20928 / 1000000;
hw.getNode("daq.timing.csr.ctrl.en_ext_sync").write(1)
>>>>>>> a1628f5b1f63ca4804f5919005d9e7f3db8ac00c
f_stat = hw.getNode("csr.stat").read();
hw.dispatch()
......@@ -57,4 +84,3 @@ print "daq.trig.csr.stat", hex(f_ctrl_2)
fw = hw.getNode("daq.timing.csr.stat.wait_sync").read();
hw.dispatch()
print "wait_sync, sync_err:", int(fw)
'''
projects/64ch/software/spi_test.py
View file @ f98014ca
......@@ -7,10 +7,8 @@ import random
from I2CuHal import I2CCore
uhal.setLogLevelTo(uhal.LogLevel.ERROR)
hw = uhal.getDevice("board", "ipbusudp-2.0://192.168.235.50:50001", "file://addrtab/top.xml")
#hw.getNode("csr.ctrl.soft_rst").write(1) # Reset ipbus registers
#hw.dispatch()
manager = uhal.ConnectionManager("file://connections.xml")
hw = manager.getDevice(sys.argv[1])
spi = hw.getNode("io.spi")
spi.getNode("divider").write(0xf) # Divide 31.25MHz ipbus clock by 32
......
projects/64ch/software/test_links.py 0 → 100755
View file @ f98014ca
#!/usr/bin/python
import uhal
import time
import sys
uhal.setLogLevelTo(uhal.LogLevel.ERROR)
manager = uhal.ConnectionManager("file://connections.xml")
hw = manager.getDevice(sys.argv[1])
v = hw.getNode("csr.id").read();
hw.dispatch()
print "csr.id", hex(v)
vu = hw.getNode("daq.tlink.us_stat").read()
vd = hw.getNode("daq.tlink.ds_stat").read()
hw.dispatch()
print "us, ds:", hex(vu), hex(vd)
hw.getNode("daq.tlink.ctrl.rst_tx").write(1)
hw.getNode("daq.tlink.ctrl.rst_rx").write(1)
hw.getNode("daq.tlink.ctrl.en_us").write(1)
hw.getNode("daq.tlink.ctrl.en_ds").write(1)
hw.getNode("daq.tlink.ctrl.loop_us").write(0x2)
hw.getNode("daq.tlink.ctrl.loop_ds").write(0x2)
hw.dispatch()
hw.getNode("daq.tlink.ctrl.rst_tx").write(0)
hw.getNode("daq.tlink.ctrl.rst_rx").write(0)
hw.dispatch()
time.sleep(1)
vu = hw.getNode("daq.tlink.us_stat").read()
vd = hw.getNode("daq.tlink.ds_stat").read()
hw.dispatch()
print "us, ds:", hex(vu), hex(vd)
projects/64ch/software/test_links_sim.py 0 → 100755
View file @ f98014ca
#!/usr/bin/python
import uhal
import time
import sys
uhal.setLogLevelTo(uhal.LogLevel.ERROR)
manager = uhal.ConnectionManager("file://connections.xml")
hw = manager.getDevice(sys.argv[1])
hw.getNode("daq.timing.csr.ctrl.rst").write(1) # Hold clk40 domain in reset
hw.dispatch()
hw.getNode("csr.ctrl.soft_rst").write(1) # Reset ipbus registers
hw.dispatch()
v = hw.getNode("csr.id").read();
hw.dispatch()
print "csr.id", hex(v)
hw.getNode("daq.timing.csr.ctrl.cap_ctr").write(1)
hw.getNode("daq.timing.csr.ctrl.cap_ctr").write(0)
sl = hw.getNode("daq.timing.csr.sctr_l").read()
sh = hw.getNode("daq.timing.csr.sctr_h").read()
hw.dispatch()
print "Counter:", hex(int(sh) << 32 + int(sl))
vu = hw.getNode("daq.tlink.us_stat").read()
vd = hw.getNode("daq.tlink.ds_stat").read()
hw.dispatch()
print "us, ds:", hex(vu), hex(vd)
hw.getNode("daq.tlink.ctrl.rst_tx").write(1)
hw.getNode("daq.tlink.ctrl.rst_rx").write(1)
hw.getNode("daq.tlink.ctrl.en_us").write(1)
hw.getNode("daq.tlink.ctrl.en_ds").write(1)
hw.getNode("daq.tlink.ctrl.loop_us").write(0x2)
hw.getNode("daq.tlink.ctrl.loop_ds").write(0x2)
hw.dispatch()
hw.getNode("daq.tlink.ctrl.rst_tx").write(0)
hw.getNode("daq.tlink.ctrl.rst_rx").write(0)
hw.dispatch()
time.sleep(1)
vu = hw.getNode("daq.tlink.us_stat").read()
vd = hw.getNode("daq.tlink.ds_stat").read()
hw.dispatch()
print "us, ds:", hex(vu), hex(vd)
projects/8ch/firmware/hdl/payload.vhd
View file @ f98014ca
......@@ -24,6 +24,8 @@ entity payload is
clk125: in std_logic;
rst125: in std_logic;
clk200: in std_logic;
pllclk: in std_logic;
pllrefclk: in std_logic;
nuke: out std_logic;
soft_rst: out std_logic;
stealth_mode: out std_logic;
......@@ -216,6 +218,8 @@ begin
d_n => adc_d_n,
clk125 => clk125,
rst125 => rst125,
pllclk => pllclk,
pllrefclk => pllrefclk,
board_id => ctrl_board_id
);
......
projects/8ch/firmware/hdl/top_decl.vhd
View file @ f98014ca
......@@ -11,16 +11,12 @@ package top_decl is
constant MAC_ADDR: std_logic_vector(47 downto 0) := X"020ddba11503";
constant IP_ADDR: std_logic_vector(31 downto 0) := X"c0a8eb00";
constant FW_REV: std_logic_vector(15 downto 0) := X"0010";
constant FW_REV: std_logic_vector(15 downto 0) := X"0011";
constant N_CHAN: integer := 8;
constant BLK_RADIX: integer := 8; -- 256 sample blocks
constant SUPERBLK_RADIX: integer := 16; -- Superblock is 64k blocks
constant LED_BLK_RADIX: integer := 18; -- Divisor for blocks-per-led-flash
constant BUF_RADIX: integer := 11; -- One BRAM for NZS / ZS buffer
constant NZS_BLKS: integer := 2; -- Reserve two blocks of space for NZS buffer
constant ZS_BLKS: integer := 2; -- Time window for ZS buffer
constant ZS_DEL: integer := 8; -- Additional samples to form channel trigger
constant N_TRG: integer := 4; -- Number of trigger types
constant N_ZS_THRESH: integer := 4; -- Number of ZS thresholds
constant N_CHAN_TRG: integer := 3; -- Number of channel trigger bits
......
projects/8ch/firmware/sim_hdl/payload_sim.vhd
View file @ f98014ca
......@@ -107,6 +107,8 @@ begin
d_n => (others => '1'),
clk125 => clk125,
rst125 => rst125,
pllclk => '0',
pllrefclk => '0',
board_id => ctrl_board_id
);
......
projects/8ch/firmware/sim_hdl/top_decl.vhd
View file @ f98014ca
......@@ -15,12 +15,8 @@ package top_decl is
constant N_CHAN: integer := 2;
constant BLK_RADIX: integer := 8; -- 256 sample blocks
constant SUPERBLK_RADIX: integer := 5; -- Superblock is 32 blocks
constant LED_BLK_RADIX: integer := 18; -- Divisor for blocks-per-led-flash
constant BUF_RADIX: integer := 11; -- One BRAM for NZS / ZS buffer
constant NZS_BLKS: integer := 2; -- Reserve two blocks of space for NZS buffer
constant ZS_BLKS: integer := 2; -- Time window for ZS buffer
constant ZS_DEL: integer := 8; -- Additional samples to form channel trigger
constant N_TRG: integer := 4; -- Number of trigger types
constant N_ZS_THRESH: integer := 4; -- Number of ZS thresholds
constant N_CHAN_TRG: integer := 3; -- Number of channel trigger bits
......
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