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euro-adc-65m-14b-40cha-gw
Commit f610bc0e authored by Dave Newbold's avatar Dave Newbold
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Syntax fixes

parent f8778abb
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Showing with 7 additions and 7 deletions
components/solid/firmware/hdl/sc_trig_link.vhd
View file @ f610bc0e
......@@ -36,7 +36,7 @@ architecture rtl of sc_trig_link is
signal ctrl: ipb_reg_v(0 downto 0);
signal stat: ipb_reg_v(1 downto 0);
signal ctrl_en_us, ctrl_en_ds, ctrl_tx_rst, ctrl_rx_rst: std_logic;
signal ctrl_en_us, ctrl_en_ds, ctrl_rst_tx, ctrl_rst_rx: std_logic;
signal ctrl_loopback_us, ctrl_loopback_ds: std_logic_vector(2 downto 0);
signal rdy_us_tx, rdy_us_rx, rdy_ds_tx, rdy_ds_rx: std_logic;
signal stat_us_tx, stat_ds_tx: std_logic_vector(1 downto 0);
......@@ -79,8 +79,8 @@ begin
port map(
sysclk => clk,
en => ctrl_en_us,
tx_rst => ctrl_tx_rst,
rx_rst => ctrl_rx_rst,
tx_rst => ctrl_rst_tx,
rx_rst => ctrl_rst_rx,
tx_rdy => rdy_us_tx,
rx_rdy => rdy_us_rx,
tx_stat => stat_us_tx,
......@@ -99,8 +99,8 @@ begin
port map(
sysclk => clk,
en => ctrl_en_ds,
tx_rst => ctrl_tx_rst,
rx_rst => ctrl_rx_rst,
tx_rst => ctrl_rst_tx,
rx_rst => ctrl_rst_rx,
tx_rdy => rdy_ds_tx,
rx_rdy => rdy_ds_rx,
tx_stat => stat_ds_tx,
......
components/solid/firmware/hdl/sc_trig_mgt_wrapper.vhd
View file @ f610bc0e
......@@ -24,7 +24,7 @@ entity sc_trig_mgt_wrapper is
txd: in std_logic_vector(15 downto 0);
txk: in std_logic_vector(1 downto 0);
rxd: out std_logic_vector(15 downto 0);
rxk: out std_logic_vector(1 downto 0);
rxk: out std_logic_vector(1 downto 0)
);
end sc_trig_mgt_wrapper;
......@@ -205,7 +205,7 @@ begin
gt0_txbufstatus_out => tx_stat,
gt0_gtptxn_out => open, -- Auto-connected by tools
gt0_gtptxp_out => open,
gt0_txoutclk_out => clk125,
gt0_txoutclk_out => open, -- Use the txoutclk from the ethernet core
gt0_txoutclkfabric_out => open,
gt0_txoutclkpcs_out => open,
gt0_txresetdone_out => open, -- Use FSM signals for monitoring
......
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