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euro-adc-65m-14b-40cha
euro-adc-65m-14b-40cha-gw
Commits
f431003d
Commit
f431003d
authored
Oct 14, 2017
by
Dave Newbold
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Adding setup script for timing board
parent
5c449d1d
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2 changed files
with
28 additions
and
1 deletion
+28
-1
top.xml
projects/timing/addr_table/top.xml
+0
-1
setup.py
projects/timing/software/setup.py
+28
-0
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projects/timing/addr_table/top.xml
View file @
f431003d
...
...
@@ -13,7 +13,6 @@
<node
id=
"trig_out_ctr"
address=
"0x6"
/>
<node
id=
"trig_in_ctr"
address=
"0x7"
/>
</node>
<node
id=
"sync_ctrl"
address=
"0x8"
fwinfo=
"endpoint;width=0"
>
<node
id=
"en_sync"
mask=
"0x1"
/>
<node
id=
"en_trig_out"
mask=
"0x2"
/>
...
...
projects/timing/software/setup.py
0 → 100755
View file @
f431003d
#!/usr/bin/python
import
uhal
import
time
import
sys
from
I2CuHal
import
I2CCore
from
si5344
import
si5344
uhal
.
setLogLevelTo
(
uhal
.
LogLevel
.
ERROR
)
hw
=
uhal
.
getDevice
(
"board"
,
"ipbusudp-2.0://192.168.235.199:50001"
,
"file://addrtab/top.xml"
)
hw
.
getNode
(
"csr.ctrl.soft_rst"
)
.
write
(
1
)
# Reset ipbus registers
hw
.
dispatch
()
clock_I2C
=
I2CCore
(
hw
,
10
,
5
,
"i2c"
,
None
)
zeClock
=
si5344
(
clock_I2C
)
res
=
zeClock
.
getDeviceVersion
()
regCfgList
=
zeClock
.
parse_clk
(
"Si5344-RevD-SCLKMA02-Registers.txt"
)
# CHANGE THE NAME OF THIS FILE
zeClock
.
writeConfiguration
(
regCfgList
)
hw
.
getNode
(
"freq_ctr.ctrl.chan_sel"
)
.
write
(
0
);
hw
.
getNode
(
"freq_ctr.ctrl.en_crap_mode"
)
.
write
(
0
);
hw
.
dispatch
()
time
.
sleep
(
2
)
fq
=
hw
.
getNode
(
"freq_ctr.freq.count"
)
.
read
();
fv
=
hw
.
getNode
(
"freq_ctr.freq.valid"
)
.
read
();
hw
.
dispatch
()
print
"Freq:"
,
int
(
fv
),
int
(
fq
)
*
119.20928
/
1000000
;
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