Adding test output

f3e359aa · Dave Newbold · dd59b6a7 · f3e359aa
Commit f3e359aa authored Nov 25, 2017 by Dave Newbold
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sc_channels.vhd components/solid/firmware/hdl/sc_channels.vhd +2 -2

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--- a/components/solid/firmware/hdl/sc_channels.vhd
+++ b/components/solid/firmware/hdl/sc_channels.vhd
@@ -27,8 +27,8 @@ entity sc_channels is
 		rst40: in std_logic;
 		clk160: in std_logic;
 		clk280: in std_logic;
-		d_p: in std_logic_vector(N_CHAN - 1 downto 0);
-		d_n: in std_logic_vector(N_CHAN - 1 downto 0);
+		d_p: inout std_logic_vector(N_CHAN - 1 downto 0);
+		d_n: inout std_logic_vector(N_CHAN - 1 downto 0);
 		sync_ctrl: in std_logic_vector(3 downto 0);
 		zs_sel: in std_logic_vector(1 downto 0);
 		sctr: in std_logic_vector(47 downto 0);