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euro-adc-65m-14b-40cha-gw
Commit de1edadd authored by Dave Newbold's avatar Dave Newbold
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Restoring cap functionality to channel buffer

parent 13a26cc9
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Showing with 11 additions and 6 deletions
components/solid/firmware/hdl/sc_chan.vhd
View file @ de1edadd
......@@ -65,7 +65,7 @@ architecture rtl of sc_chan is
signal norm_mode, pb_mode, cap_mode: std_logic;
signal d_in, d_in_i, d_buf: std_logic_vector(13 downto 0);
signal d_c: std_logic_vector(1 downto 0);
signal slip, chan_rst, buf_we, inc: std_logic;
signal slip, chan_rst, cap, inc: std_logic;
signal ctrl_en_sync, ctrl_en_buf, ctrl_invert: std_logic;
signal ctrl_mode, ctrl_src: std_logic_vector(1 downto 0);
signal cap_full, buf_full, dr_full, dr_warn: std_logic;
......@@ -117,7 +117,7 @@ begin
slip <= sync_ctrl(0) and ctrl_en_sync; -- CDC
chan_rst <= (sync_ctrl(1) and ctrl_en_sync) or rst40; -- CDC
buf_we <= sync_ctrl(2) and ctrl_en_sync; -- CDC
cap <= sync_ctrl(2) and ctrl_en_sync; -- CDC
inc <= sync_ctrl(3) and ctrl_en_sync; -- CDC
stat(0) <= X"000000" & "000" & err_i & dr_warn & dr_full & buf_full & cap_full; -- CDC
......@@ -198,6 +198,7 @@ begin
d => d_buf,
blkend => blkend,
nzs_en => nzs_en,
cap => cap,
cap_full => cap_full,
zs_thresh => zs_thresh,
zs_en => zs_en,
......
components/solid/firmware/hdl/sc_chan_buf.vhd
View file @ de1edadd
......@@ -26,6 +26,7 @@ entity sc_chan_buf is
d: in std_logic_vector(13 downto 0); -- data in; clk40 dom
blkend: in std_logic;
nzs_en: in std_logic; -- enable nzs buffer; clk40 dom
cap: in std_logic;
cap_full: out std_logic;
zs_thresh: in std_logic_vector(13 downto 0); -- ZS threshold; clk40 dom
zs_en: in std_logic; -- enable zs buffer; clk40 dom
......@@ -54,7 +55,7 @@ architecture rtl of sc_chan_buf is
signal cap_done: std_logic;
signal zctr: unsigned(BLK_RADIX - 1 downto 0);
signal z0, z1: std_logic;
signal zs_en_d, zs_en_dd, nzs_en_d, wenz, wez, rez, wez_d: std_logic;
signal zs_en_d, zs_en_dd, nzen, nzen_d, wenz, wez, rez, wez_d: std_logic;
signal go, zs_run, zs_keep, buf_full_i, p, q_blkend_i: std_logic;
begin
......@@ -109,10 +110,13 @@ begin
-- NZS pointer control
cap_run <= (cap_run or cap) and not (cap_done or buf_rst) and cap_mode;
nzen <= nzs_en or cap_run;
process(clk40)
begin
if rising_edge(clk40) then
nzs_en_d <= nzs_en;
nzen_d <= nzen;
zs_en_d <= zs_en;
zs_en_dd <= zs_en_d;
end if;
......@@ -121,7 +125,7 @@ begin
process(clk40)
begin
if falling_edge(clk40) then
if (pb_mode = '1' and nzs_en = '0') or (pb_mode = '0' and nzs_en_d = '0') then
if (pb_mode = '1' and nzen = '0') or (pb_mode = '0' and nzen_d = '0') then
pnz <= to_unsigned(0, pnz'length);
cap_done <= '0';
else
......@@ -137,7 +141,7 @@ begin
end if;
end process;
wenz <= (norm_mode or cap_mode) and nzs_en and not cap_done;
wenz <= (norm_mode or cap_mode) and nzen and not cap_done;
d_nzs <= blkend & '0' & d;
cap_full <= cap_done;
......
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