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euro-adc-65m-14b-40cha-gw
Commit dc866c0b authored by Dave Newbold's avatar Dave Newbold
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Merge branch 'master' of bitbucket.org:solidexperiment/solid_firmware

parents 71baa9e5 23905600
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Showing with 27 additions and 17 deletions
components/solid/addr_table/sc_chan.xml
View file @ dc866c0b
......@@ -36,13 +36,13 @@
</node>
<node id="t1" address="0x1">
<node id="pthresh" mask="0x3ff"/>
<node id="cthresh" mask="0x1f0000"/>
<node id="wsize" mask="0xf000000"/>
<node id="cthresh" mask="0x1ff0000"/>
<node id="wsize" mask="0xf0000000"/>
</node>
<node id="t2" address="0x2">
<node id="pthresh" mask="0x3ff"/>
<node id="cthresh" mask="0x1f0000"/>
<node id="wsize" mask="0xf000000"/>
<node id="cthresh" mask="0x1ff0000"/>
<node id="wsize" mask="0xf0000000"/>
</node>
</node>
</node>
components/solid/firmware/hdl/sc_chan.vhd
View file @ dc866c0b
......@@ -216,8 +216,9 @@ begin
ipb_out => ipbr(N_SLV_TRIG_THRESH),
clk40 => clk40,
rst40 => chan_rst,
d => d_buf,
mark => blkend,
en => nzs_en,
d => d_buf,
trig => trig
);
......
components/solid/firmware/hdl/sc_chan_trig.vhd
View file @ dc866c0b
......@@ -25,8 +25,9 @@ entity sc_chan_trig is
ipb_out: out ipb_rbus;
clk40: in std_logic;
rst40: in std_logic;
d: in std_logic_vector(13 downto 0);
mark: in std_logic;
en: in std_logic;
d: in std_logic_vector(13 downto 0);
trig: out std_logic_vector(N_CHAN_TRG - 1 downto 0)
);
......@@ -72,9 +73,10 @@ begin
clk => clk40,
rst => rst40,
clr => mark,
en => en,
d => d,
cthresh => ctrl(1)(20 downto 16),
wsize => ctrl(1)(27 downto 24),
cthresh => ctrl(1)(24 downto 16),
wsize => ctrl(1)(31 downto 28),
pthresh => ctrl(1)(VAL_WIDTH - 1 downto 0),
trig => trig(1)
);
......@@ -87,9 +89,10 @@ begin
clk => clk40,
rst => rst40,
clr => mark,
en => en,
d => d,
cthresh => ctrl(2)(20 downto 16),
wsize => ctrl(2)(27 downto 24),
cthresh => ctrl(2)(24 downto 16),
wsize => ctrl(2)(31 downto 28),
pthresh => ctrl(2)(VAL_WIDTH - 1 downto 0),
trig => trig(2)
);
......
components/solid/firmware/hdl/sc_ctrig_npeaks.vhd
View file @ dc866c0b
......@@ -17,6 +17,7 @@ entity sc_ctrig_npeaks is
clk: in std_logic;
rst: in std_logic;
clr: in std_logic;
en: in std_logic;
d: in std_logic_vector(VAL_WIDTH - 1 downto 0);
cthresh: in std_logic_vector(8 downto 0);
wsize: in std_logic_vector(3 downto 0);
......@@ -29,11 +30,13 @@ end sc_ctrig_npeaks;
architecture rtl of sc_ctrig_npeaks is
signal d1, d2: std_logic_vector(VAL_WIDTH - 1 downto 0);
signal p: std_logic;
signal p, rsti: std_logic;
signal count: std_logic_vector(cthresh'range);
begin
rsti <= rst or not en;
d1 <= d when rising_edge(clk);
d2 <= d1 when rising_edge(clk);
p <= '1' when unsigned(d1) > unsigned(pthresh) and unsigned(d2) < unsigned(d1) and unsigned(d) <= unsigned(d1) else '0';
......@@ -44,7 +47,7 @@ begin
)
port map(
clk => clk,
rst => rst,
rst => rsti,
wsize => wsize,
p => p,
count => count
......@@ -57,7 +60,7 @@ begin
)
port map(
clk => clk,
rst => rst,
rst => rsti,
clr => clr,
d => count,
threshold => cthresh,
......
components/solid/firmware/hdl/sc_ctrig_tot.vhd
View file @ dc866c0b
......@@ -17,6 +17,7 @@ entity sc_ctrig_tot is
clk: in std_logic;
rst: in std_logic;
clr: in std_logic;
en: in std_logic;
d: in std_logic_vector(VAL_WIDTH - 1 downto 0);
cthresh: in std_logic_vector(8 downto 0);
wsize: in std_logic_vector(3 downto 0);
......@@ -28,11 +29,13 @@ end sc_ctrig_tot;
architecture rtl of sc_ctrig_tot is
signal p: std_logic;
signal p, rsti: std_logic;
signal count: std_logic_vector(cthresh'range);
begin
rsti <= rst or not en;
p <= '1' when unsigned(d) > unsigned(pthresh) else '0';
cnt: entity work.sc_ctrig_window
......@@ -41,7 +44,7 @@ begin
)
port map(
clk => clk,
rst => rst,
rst => rsti,
wsize => wsize,
p => p,
count => count
......@@ -53,7 +56,7 @@ begin
)
port map(
clk => clk,
rst => rst,
rst => rsti,
clr => clr,
d => count,
threshold => cthresh,
......
components/solid/firmware/hdl/sc_ctrig_window.vhd
View file @ dc866c0b
......@@ -37,7 +37,7 @@ architecture rtl of sc_ctrig_window is
begin
w(0) <= p;
w(0) <= p and not rst;
dgen: for i in 2 ** wsize'length - 1 downto 0 generate
......
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