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euro-adc-65m-14b-40cha-gw
Commit c59d7782 authored by Dave Newbold's avatar Dave Newbold
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Merging changes from master

parents 0ee470e5 cc2335bd
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Showing with 10 additions and 5 deletions
projects/timing/firmware/hdl/payload.vhd
View file @ c59d7782
...@@ -6,7 +6,8 @@ use ieee.numeric_std.all; ...@@ -6,7 +6,8 @@ use ieee.numeric_std.all;
use ieee.std_logic_misc.all; use ieee.std_logic_misc.all;
use work.ipbus.all; use work.ipbus.all;
use work.ipbus_decode_top.all; use work.ipbus_decode_top.all;
use work.ipbus_reg_types.all;
entity payload is entity payload is
port( port(
...@@ -204,6 +205,7 @@ begin ...@@ -204,6 +205,7 @@ begin
sda_i_p => sda_i_p, sda_i_p => sda_i_p,
sda_i_n => sda_i_n, sda_i_n => sda_i_n,
busy_o => trig_out_us, busy_o => trig_out_us,
busy_o => ctrl_busy,
busy_o_p => busy_o_p, busy_o_p => busy_o_p,
busy_o_n => busy_o_n, busy_o_n => busy_o_n,
busy_i => trig_in_ds, busy_i => trig_in_ds,
...@@ -221,8 +223,8 @@ begin ...@@ -221,8 +223,8 @@ begin
ctr: entity work.freq_ctr ctr: entity work.freq_ctr
port map( port map(
clk => clk, clk => ipb_clk,
rst => rst, rst => ipb_rst,
ipb_in => ipbw(N_SLV_FREQ_CTR), ipb_in => ipbw(N_SLV_FREQ_CTR),
ipb_out => ipbr(N_SLV_FREQ_CTR), ipb_out => ipbr(N_SLV_FREQ_CTR),
clkdiv => clkdiv clkdiv => clkdiv
......
projects/timing/firmware/hdl/sc_timing_iobufs.vhd
View file @ c59d7782
...@@ -61,6 +61,7 @@ end sc_timing_iobufs; ...@@ -61,6 +61,7 @@ end sc_timing_iobufs;
architecture rtl of sc_timing_iobufs is architecture rtl of sc_timing_iobufs is
signal clk_o, clk_i_u: std_logic; signal clk_o, clk_i_u: std_logic;
signal sda_i_inv: std_logic;
begin begin
...@@ -162,8 +163,10 @@ begin ...@@ -162,8 +163,10 @@ begin
port map( port map(
i => sda_i_p, i => sda_i_p,
ib => sda_i_n, ib => sda_i_n,
o => sda_i o => sda_i_inv
); );
sda_i <= not sda_i_inv;
obuf_busy_o: OBUFDS obuf_busy_o: OBUFDS
port map( port map(
......
projects/timing/firmware/ucf/pc054_ax3_pm3.tcl
View file @ c59d7782
...@@ -3,7 +3,7 @@ set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] ...@@ -3,7 +3,7 @@ set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
create_clock -period 25.0 -name clk_i [get_ports clk_i_p] create_clock -period 25.0 -name clk_i [get_ports clk_i_p]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks fmc_clk] -group [get_clocks -include_generated_clocks rec_clk] -group [get_clocks -include_generated_clocks -of_obj [get_pins -of_obj [get_cells infra/clocks/mmcm] -filter {NAME =~ *CLKOUT*}]] set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks clk_i]
set_property IOSTANDARD LVDS_25 [get_port {clk_rstn_* clk_o_* clk_i_* trig_o_* trig_i_* sync_o_* sync_i_* trig_sel_* sync_sel_* scl_* sda_* busy_o_* busy_i_*}] set_property IOSTANDARD LVDS_25 [get_port {clk_rstn_* clk_o_* clk_i_* trig_o_* trig_i_* sync_o_* sync_i_* trig_sel_* sync_sel_* scl_* sda_* busy_o_* busy_i_*}]
set_property DIFF_TERM TRUE [get_port {clk_rstn_* clk_o_* clk_i_* trig_o_* trig_i_* sync_o_* sync_i_* trig_sel_* sync_sel_* scl_* sda_* busy_o_* busy_i_*}] set_property DIFF_TERM TRUE [get_port {clk_rstn_* clk_o_* clk_i_* trig_o_* trig_i_* sync_o_* sync_i_* trig_sel_* sync_sel_* scl_* sda_* busy_o_* busy_i_*}]
......
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