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euro-adc-65m-14b-40cha-gw
Commit 9e608510 authored by Dave Newbold's avatar Dave Newbold
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Changing counter logic

parent 11ace841
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Showing with 11 additions and 4 deletions
components/solid/firmware/hdl/sc_chan.vhd
View file @ 9e608510
......@@ -70,6 +70,7 @@ architecture rtl of sc_chan is
signal ctrl_en_sync, ctrl_en_buf, ctrl_invert: std_logic;
signal ctrl_mode, ctrl_src: std_logic_vector(1 downto 0);
signal cap_full, buf_full, dr_full, dr_warn: std_logic;
signal sctr_p: std_logic_vector(11 downto 0);
signal dr_d: std_logic_vector(31 downto 0);
signal ro_en, keep_i, flush_i, err_i, req, blkend, dr_blkend, dr_wen: std_logic;
......@@ -138,11 +139,17 @@ begin
);
d_in_i <= d_in when ctrl_invert = '0' else not d_in;
with sctr(1 downto 0) select sctr_p <=
sctr(11 downto 0) when "00",
sctr(23 downto 12) when "01",
sctr(35 downto 24) when "10",
sctr(47 downto 36) when others;
with ctrl_src select d_buf <=
d_in_i when "00",
d_test when "01",
sctr when "10",
"00" & sctr_p when "10",
fake when others;
-- Channel status
......
components/solid/firmware/hdl/sc_local_trig.vhd
View file @ 9e608510
......@@ -196,7 +196,7 @@ begin
-- Trigger data to readout
go <= (go or (ro_go and ((or_reduce(tc) and not rveto) or last_gasp or hoorah))) and not blkend and trig_en when rising_edge(clk40);
go <= (go or (ro_go and ((or_reduce(tc) and not rveto) or last_gasp or hoorah))) and not blkend and trig_en and not rst40 when rising_edge(clk40);
blkend <= '1' when unsigned(ro_ctr) = 3 + 2 * N_CHAN_TRG else '0';
ro_valid <= go;
ro_blkend <= blkend;
......@@ -208,7 +208,7 @@ begin
with ro_ctr select ro_q <=
X"100" & "00" & last_gasp & hoorah & (15 downto N_TRG => '0') & tc when X"00", -- Type 1
std_logic_vector(sctr(31 downto 0)) when X"01",
std_logic_vector(sctr(31 downto BLK_RADIX)) & (BLK_RADIX - 1 downto 0 => '0') when X"01",
X"0000" & std_logic_vector(sctr(47 downto 32)) when X"02",
X"00000000" when X"03",
b when others;
......
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