Merge branch 'master' of https://bitbucket.org/solidexperiment/solid_firmware

9be153cf · Dave Newbold · ed70a4fe · f322a4b0 · 9be153cf · 9be153cf
Commit 9be153cf authored Apr 10, 2018 by Dave Newbold
9 changed files
--- a/components/solid/addr_table/sc_trig.xml
+++ b/components/solid/addr_table/sc_trig.xml
@@ -4,6 +4,7 @@
 			<node id="dtmon_en" mask="0x1"/>
 			<node id="trig_in_en" mask="0x2"/>
 			<node id="trig_out_force" mask="0x4"/>
+			<node id="coinc_mode" mask="0x8"/>
 		</node>
 		<node id="evt_ctr" address="0x2"/>
 		<node id="stat" address="0x3">

--- a/components/solid/firmware/cfg/sc_trig.dep
+++ b/components/solid/firmware/cfg/sc_trig.dep
 src sc_trig.vhd sc_local_trig.vhd sc_zs_sel_rolling.vhd sc_trig_ro_block.vhd sc_deadtime_mon.vhd 
-src sc_trig_gen.vhd sc_trig_gen_or.vhd
+src sc_trig_gen.vhd sc_trig_gen_or.vhd sc_trig_gen_or_coinc.vhd sc_trig_stretch.vhd
 include sc_seq.dep
 src ipbus_decode_sc_trig.vhd
 addrtab -t sc_trig.xml

--- a/components/solid/firmware/hdl/sc_local_trig.vhd
+++ b/components/solid/firmware/hdl/sc_local_trig.vhd
@@ -19,6 +19,7 @@ entity sc_local_trig is
 		clk40: in std_logic;
 		rst40: in std_logic;
 		en: in std_logic;
+		coinc_mode: in std_logic;
 		mask: in std_logic_vector(N_TRG - 1 downto 0);
 		hops: in std_logic_vector(31 downto 0);
 		mark: in std_logic;
@@ -55,7 +56,7 @@ begin
 	
 -- Threshold trigger generator

-	tg0: entity work.sc_trig_gen_or
+	tg0: entity work.sc_trig_gen_or_coinc
 		generic map(
 			TBIT => 0,
 			DELAY => 2
@@ -63,6 +64,7 @@ begin
 		port map(
 			clk => clk40,
 			en => en,
+			mode => coinc_mode,
 			mark => mark,
 			chan_trig => chan_trig,
 			chan_act => cact(0),

--- a/components/solid/firmware/hdl/sc_trig.vhd
+++ b/components/solid/firmware/hdl/sc_trig.vhd
@@ -56,7 +56,7 @@ architecture rtl of sc_trig is
 	signal ctrl, ctrl_mask: ipb_reg_v(0 downto 0);
 	signal stat: ipb_reg_v(1 downto 0);
 	signal stb: std_logic_vector(0 downto 0);
-	signal ctrl_dtmon_en, ctrl_trig_in_en, ctrl_trig_out_force: std_logic;
+	signal ctrl_dtmon_en, ctrl_trig_in_en, ctrl_trig_out_force, ctrl_coinc_mode: std_logic;
 	signal masks: ipb_reg_v(N_CHAN_TRG * 2 - 1 downto 0);
 	signal trig_mask: std_logic_vector(N_TRG - 1 downto 0);
 	signal hop_cfg: std_logic_vector(31 downto 0);
@@ -109,6 +109,7 @@ begin
 	ctrl_dtmon_en <= ctrl(0)(0);
 	ctrl_trig_in_en <= ctrl(0)(1);
 	ctrl_trig_out_force <= ctrl(0)(2) and stb(0);
+	ctrl_coinc_mode <= ctrl(0)(3);
 	stat(0) <= X"0" & tctr;
 	stat(1) <= X"0000000" & "00" & rveto & err;

@@ -183,6 +184,7 @@ begin
 			clk40 => clk40,
 			rst40 => rst40,
 			en => trig_en,
+			coinc_mode => ctrl_coinc_mode,
 			mask => trig_mask,
 			hops => hop_cfg,
 			mark => mark,

--- a/components/solid/firmware/hdl/sc_trig_gen_or_coinc.vhd
+++ b/components/solid/firmware/hdl/sc_trig_gen_or_coinc.vhd
+-- sc_trig_gen_or_coinc
+--
+-- Local trigger module for simple 'ored' threshold triggers
+-- This trigger will fire if any channel has a high bit in a given block
+-- Can be set up to require a coincidence between X and Y channels
+--
+-- Dave Newbold, March 2018
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use ieee.std_logic_misc.all;
+
+use work.top_decl.all;
+
+entity sc_trig_gen_or_coinc is
+	generic(
+		TBIT: natural := 0;
+		DELAY: positive := 1
+	);
+	port(
+		clk: in std_logic;
+		en: in std_logic;
+		mode: in std_logic;
+		mark: in std_logic;
+		chan_trig: in sc_trig_array;
+		hit: out std_logic;
+		chan_act: out std_logic_vector(N_CHAN - 1 downto 0);
+		valid: out std_logic;
+		ack: in std_logic
+	);
+
+end sc_trig_gen_or_coinc;
+
+architecture rtl of sc_trig_gen_or_coinc is
+
+	signal y_or, x_or: std_logic;
+	signal t, m, tc, v: std_logic;
+	signal mark_del: std_logic_vector(DELAY downto 0);
+	signal c: std_logic_vector(N_CHAN - 1 downto 0);
+
+begin
+
+-- Define the trigger condition
+
+	process(chan_trig)
+	begin
+		y_or <= '0';
+		x_or <= '0';
+		for i in range N_CHAN / 4 - 1 downto 0 loop
+			y_or <= y_or or chan_trig(TBIT)(SC_CH_Y0(i)) or chan_trig(TBIT)(SC_CH_Y1(i));
+			x_or <= x_or or chan_trig(TBIT)(SC_CH_X0(i)) or chan_trig(TBIT)(SC_CH_X1(i));
+		end loop;
+	end process;
+	
+	stretch: entity work.sc_trig_stretch
+		generic map(
+			WIDTH => 2
+		)
+		port map(
+			clk => clk,
+			del => "0011", -- Fixed four-sample window for now
+			d(0) => y_or,
+			d(1) => x_or,
+			q(0) => y_or_s,
+			q(1) => x_or_s
+		);
+
+	t <= (y_or_s and x_or_s) when mode = '1' else or_reduce(chan_trig(TBIT));
+		
+-- Define the block boundary
+
+	mark_del <= mark_del(DELAY - 1 downto 0) & mark when rising_edge(clk);
+	m <= mark_del(DELAY);
+	
+-- Catch a trigger feature with the block
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if en = '0' then
+				tc <= '0';
+				c <= (others => '0');
+			elsif t = '1' then
+				tc <= '1';
+				if m = '0' then
+					c <= c or chan_trig(TBIT);
+				else
+					c <= chan_trig(TBIT);
+				end if;
+			elsif m = '1' then
+				tc <= '0';
+				c <= (others => '0');
+			end if;
+		end if;
+	end process;
+				
+-- Trigger request output
+
+	hit <= t;
+	v <= (v or (tc and m)) and not (mark or ack or not en) when rising_edge(clk);
+	valid <= v;
+	chan_act <= c when m = '1' and rising_edge(clk);
+	
+end rtl;
--- a/components/solid/firmware/hdl/sc_trig_stretch.vhd
+++ b/components/solid/firmware/hdl/sc_trig_stretch.vhd
+-- sc_trig_stretch
+--
+-- Pulse stretcher for trigger coincidence
+--
+-- Dave Newbold, March 2018
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+entity sc_trig_stretch is
+	generic(
+		WIDTH: positive := 1
+	);
+	port(
+		clk: in std_logic;
+		del: in std_logic_vector(3 downto 0);
+		d: in std_logic_vector(WIDTH - 1 downto 0);
+		q: out std_logic_vector(WIDTH - 1 downto 0)
+	);
+
+end sc_trig_stretch;
+
+architecture rtl of sc_trig_stretch is
+
+	type r_t: array(2 ** del'width - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
+	signal r: r_t;
+	
+begin
+	
+	r(0) <= d;
+	r(r'left downto 1) <= r(r'left - 1 downto 0) when rising_edge(clk);
+	q <= r(to_integer(unsigned(del)));
+
+end rtl;
--- a/components/solid/firmware/hdl/sc_zs_sel_rolling.vhd
+++ b/components/solid/firmware/hdl/sc_zs_sel_rolling.vhd
@@ -2,8 +2,8 @@
 --
 -- Zero suppression threshold select logic - range of blocks
 -- 
-- zscfg is four bits for each trigger type
-- b3-2: blocks for change threshold for (from start of nzs buffer)
+-- zscfg is eight bits for each trigger type
+-- b7-4: blocks for change threshold for (from start of nzs buffer)
 -- b1-0: ZS threshold ID for this trigger
 --
 -- Dave Newbold, August 2016

--- a/projects/64ch/firmware/hdl/top_decl.vhd
+++ b/projects/64ch/firmware/hdl/top_decl.vhd
@@ -11,7 +11,7 @@ package top_decl is
  
 	constant MAC_ADDR: std_logic_vector(47 downto 0) := X"020ddba11500"; -- last byte from local addr
 	constant IP_ADDR: std_logic_vector(31 downto 0) := X"c0a8eb00"; -- last byte from local addr
-	constant FW_REV: std_logic_vector(15 downto 0) := X"0013";
+	constant FW_REV: std_logic_vector(15 downto 0) := X"0015";

 	constant N_CHAN: integer := 64;
 	constant BLK_RADIX: integer := 8; -- 256 sample blocks
@@ -26,4 +26,10 @@ package top_decl is
 	type sc_trig_array is array(N_CHAN_TRG - 1 downto 0) of std_logic_vector(N_CHAN - 1 downto 0);
 	type sc_ltrig_array is array(N_TRG - 1 downto 0) of std_logic_vector(N_CHAN - 1 downto 0);
 	
+	type sc_ch_array_t is array(N_CHAN / 4 - 1 downto 0) of integer;
+	constant SC_CH_Y0: sc_ch_array_t: (24, 25, 26, 27, 28, 29, 30, 31, 0, 1, 2, 3, 4, 5, 6, 7);
+	constant SC_CH_Y1: sc_ch_array_t: (39, 38, 37, 36, 35, 34, 33, 32, 63, 62, 61, 60, 59, 58, 57, 56);
+	constant SC_CH_X0: sc_ch_array_t: (23, 22, 21, 20, 19, 18, 17, 16, 47, 46, 45, 44, 43, 42, 41, 40);
+	constant SC_CH_X1: sc_ch_array_t: (8, 9, 10, 11, 12, 13, 14, 15, 48, 49, 50, 51, 52, 53, 54, 55);
+	
 end top_decl;
--- a/projects/8ch/firmware/hdl/top_decl.vhd
+++ b/projects/8ch/firmware/hdl/top_decl.vhd
@@ -11,7 +11,7 @@ package top_decl is
  
 	constant MAC_ADDR: std_logic_vector(47 downto 0) := X"020ddba11503";
 	constant IP_ADDR: std_logic_vector(31 downto 0) := X"c0a8eb00";
-	constant FW_REV: std_logic_vector(15 downto 0) := X"0013";
+	constant FW_REV: std_logic_vector(15 downto 0) := X"0015";

 	constant N_CHAN: integer := 8;
 	constant BLK_RADIX: integer := 8; -- 256 sample blocks