Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
E
euro-adc-65m-14b-40cha-gw
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
eurocard
euro-adc-65m-14b-40cha
euro-adc-65m-14b-40cha-gw
Commits
6893f4d2
Commit
6893f4d2
authored
Jul 14, 2017
by
Dave Newbold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Adding alignment led
parent
241d34c7
Show whitespace changes
Inline
Side-by-side
Showing
6 changed files
with
13 additions
and
7 deletions
+13
-7
pc051a_infra.vhd
boards/pc051a/base_fw/synth/firmware/hdl/pc051a_infra.vhd
+2
-2
top_pc051a.vhd
boards/pc051a/base_fw/synth/firmware/hdl/top_pc051a.vhd
+2
-2
sc_daq.vhd
components/solid/firmware/hdl/sc_daq.vhd
+2
-0
sc_timing.vhd
components/solid/firmware/hdl/sc_timing.vhd
+3
-1
payload.vhd
projects/8ch/firmware/hdl/payload.vhd
+3
-2
top_decl.vhd
projects/8ch/firmware/hdl/top_decl.vhd
+1
-0
No files found.
boards/pc051a/base_fw/synth/firmware/hdl/pc051a_infra.vhd
View file @
6893f4d2
...
...
@@ -81,9 +81,9 @@ begin
q
=>
led_p
);
leds
<=
(
'0'
,
onehz
);
leds
<=
(
led_p
(
0
),
locked
&
onehz
);
debug
<=
sfp_los
&
'0'
&
led_p
(
0
)
&
(
locked
and
onehz
);
debug
<=
(
others
=>
'0'
);
-- Ethernet MAC core and PHY interface
...
...
boards/pc051a/base_fw/synth/firmware/hdl/top_pc051a.vhd
View file @
6893f4d2
...
...
@@ -86,7 +86,7 @@ begin
nuke
=>
nuke
,
soft_rst
=>
soft_rst
,
leds
=>
leds
(
1
downto
0
),
debug
=>
leds_c
,
debug
=>
open
,
mac_addr
(
47
downto
4
)
=>
MAC_ADDR
(
47
downto
4
),
mac_addr
(
3
downto
0
)
=>
dip_sw
,
ip_addr
(
31
downto
4
)
=>
IP_ADDR
(
31
downto
4
),
...
...
@@ -110,7 +110,7 @@ begin
clk200
=>
clk200
,
nuke
=>
nuke
,
soft_rst
=>
soft_rst
,
userleds
=>
open
,
userleds
=>
leds_c
,
si5326_scl
=>
si5326_scl
,
si5326_sda_o
=>
si5326_sda_o
,
si5326_sda_i
=>
si5326_sda
,
...
...
components/solid/firmware/hdl/sc_daq.vhd
View file @
6893f4d2
...
...
@@ -26,6 +26,7 @@ entity sc_daq is
sync_in
:
in
std_logic
;
trig_in
:
in
std_logic
;
trig_out
:
out
std_logic
;
led_out
:
out
std_logic
;
chan
:
in
std_logic_vector
(
7
downto
0
);
chan_err
:
out
std_logic
;
d_p
:
in
std_logic_vector
(
N_CHAN
-
1
downto
0
);
...
...
@@ -92,6 +93,7 @@ begin
clk280
=>
clk280
,
sync_in
=>
sync_in
,
trig_in
=>
trig_in
,
led_out
=>
led_out
,
sctr
=>
sctr
,
chan_sync_ctrl
=>
sync_ctrl
,
trig_en
=>
trig_en
,
...
...
components/solid/firmware/hdl/sc_timing.vhd
View file @
6893f4d2
...
...
@@ -30,6 +30,7 @@ entity sc_timing is
clk280
:
out
std_logic
;
-- chip 280MHz clock
sync_in
:
in
std_logic
;
-- external sync signal in
trig_in
:
in
std_logic
;
-- external trigger in
led_out
:
out
std_logic
;
-- LED flash out
sctr
:
out
std_logic_vector
(
47
downto
0
);
-- sample counter
chan_sync_ctrl
:
out
std_logic_vector
(
3
downto
0
);
-- Timing signals to channels
trig_en
:
out
std_logic
;
...
...
@@ -176,6 +177,7 @@ begin
end
process
;
sctr
<=
std_logic_vector
(
sctr_i
);
led_out
<=
sctr
(
LED_BLK_RADIX
+
BLK_RADIX
-
1
);
-- Random number gen
...
...
projects/8ch/firmware/hdl/payload.vhd
View file @
6893f4d2
...
...
@@ -73,7 +73,7 @@ architecture rtl of payload is
signal
ctrl_rst_mmcm
,
locked
,
idelayctrl_rdy
,
ctrl_rst_idelayctrl
,
ctrl_sync_mode
:
std_logic
;
signal
ctrl_chan
:
std_logic_vector
(
7
downto
0
);
signal
ctrl_board_id
:
std_logic_vector
(
7
downto
0
);
signal
chan_err
:
std_logic
;
signal
chan_err
,
led
:
std_logic
;
begin
...
...
@@ -119,7 +119,7 @@ begin
ctrl_chan
<=
ctrl
(
0
)(
15
downto
8
);
ctrl_board_id
<=
ctrl
(
0
)(
23
downto
16
);
userleds
<=
"000
0"
;
userleds
<=
"000
"
&
led
;
-- Required for timing alignment at inputs
...
...
@@ -206,6 +206,7 @@ begin
sync_in
=>
sync_in
,
trig_in
=>
trig_in
,
trig_out
=>
trig_out
,
led_out
=>
led
,
chan
=>
ctrl_chan
,
chan_err
=>
chan_err
,
d_p
=>
adc_d_p
,
...
...
projects/8ch/firmware/hdl/top_decl.vhd
View file @
6893f4d2
...
...
@@ -16,6 +16,7 @@ package top_decl is
constant
N_CHAN
:
integer
:
=
8
;
constant
BLK_RADIX
:
integer
:
=
8
;
-- 256 sample blocks
constant
SUPERBLK_RADIX
:
integer
:
=
16
;
-- Superblock is 64k blocks
constant
LED_BLK_RADIX
:
integer
:
=
18
;
-- Divisor for blocks-per-led-flash
constant
BUF_RADIX
:
integer
:
=
11
;
-- One BRAM for NZS / ZS buffer
constant
NZS_BLKS
:
integer
:
=
2
;
-- Reserve two blocks of space for NZS buffer
constant
ZS_BLKS
:
integer
:
=
2
;
-- Time window for ZS buffer
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment