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euro-adc-65m-14b-40cha-gw
Commit 241d34c7 authored by Dave Newbold's avatar Dave Newbold
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Fixing syntax errors

parent a8b8f90e
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Showing with 28 additions and 20 deletions
boards/pc051a/base_fw/synth/firmware/hdl/top_pc051a.vhd
View file @ 241d34c7
......@@ -134,12 +134,12 @@ begin
analog_scl => analog_scl,
analog_sda_o => analog_sda_o,
analog_sda_i => analog_sda,
sync_in_p => sync_a_p,
sync_in_n => sync_a_n,
trig_in_p => sync_b_p,
trig_in_n => sync_b_n,
trig_out_p => sync_c_p,
trig_out_n => sync_c_n,
sync_in_p => sync_in_p,
sync_in_n => sync_in_n,
trig_in_p => trig_in_p,
trig_in_n => trig_in_n,
trig_out_p => trig_out_p,
trig_out_n => trig_out_n,
clk_pll_p => clk_pll_p,
clk_pll_n => clk_pll_n
);
......
boards/pc051a/base_fw/synth/firmware/ucf/pc051a.tcl
View file @ 241d34c7
......@@ -99,7 +99,7 @@ set_property IOSTANDARD LVDS_25 [get_ports {clk40_*}]
set_property PACKAGE_PIN W11 [get_ports {clk40_p}]
set_property PACKAGE_PIN W12 [get_ports {clk40_n}]
set_property IOSTANDARD LVDS_25 [get_ports {sync_*}]
set_property IOSTANDARD LVDS_25 [get_ports {trig_out_* trig_in_* sync_in_*}]
set_property PACKAGE_PIN J15 [get_ports {trig_out_p}]
set_property PACKAGE_PIN H15 [get_ports {trig_out_n}]
set_property PACKAGE_PIN G17 [get_ports {trig_in_p}]
......
components/solid/firmware/hdl/ipbus_decode_sc_trig.vhd
View file @ 241d34c7
......@@ -17,13 +17,14 @@ package ipbus_decode_sc_trig is
subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
function ipbus_sel_sc_trig(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-- START automatically generated VHDL the Tue Jun 20 13:47:26 2017
-- START automatically generated VHDL the Fri Jul 14 14:14:53 2017
constant N_SLV_CSR: integer := 0;
constant N_SLV_LOC_MASK: integer := 1;
constant N_SLV_DTMON: integer := 2;
constant N_SLV_SEQ: integer := 3;
constant N_SLV_CHAN_MASK: integer := 4;
constant N_SLAVES: integer := 5;
constant N_SLV_ZS_CFG: integer := 2;
constant N_SLV_DTMON: integer := 3;
constant N_SLV_SEQ: integer := 4;
constant N_SLV_CHAN_MASK: integer := 5;
constant N_SLAVES: integer := 6;
-- END automatically generated VHDL
......@@ -35,11 +36,13 @@ package body ipbus_decode_sc_trig is
variable sel: ipbus_sel_t;
begin
-- START automatically generated VHDL the Tue Jun 20 13:47:26 2017
-- START automatically generated VHDL the Fri Jul 14 14:14:53 2017
if std_match(addr, "---------------------------000--") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000000 / mask 0x0000001c
elsif std_match(addr, "---------------------------0010-") then
sel := ipbus_sel_t(to_unsigned(N_SLV_LOC_MASK, IPBUS_SEL_WIDTH)); -- loc_mask / base 0x00000004 / mask 0x0000001e
elsif std_match(addr, "---------------------------00100") then
sel := ipbus_sel_t(to_unsigned(N_SLV_LOC_MASK, IPBUS_SEL_WIDTH)); -- loc_mask / base 0x00000004 / mask 0x0000001f
elsif std_match(addr, "---------------------------00101") then
sel := ipbus_sel_t(to_unsigned(N_SLV_ZS_CFG, IPBUS_SEL_WIDTH)); -- zs_cfg / base 0x00000005 / mask 0x0000001f
elsif std_match(addr, "---------------------------0011-") then
sel := ipbus_sel_t(to_unsigned(N_SLV_DTMON, IPBUS_SEL_WIDTH)); -- dtmon / base 0x00000006 / mask 0x0000001e
elsif std_match(addr, "---------------------------01---") then
......
components/solid/firmware/hdl/sc_local_trig.vhd
View file @ 241d34c7
......@@ -19,7 +19,7 @@ entity sc_local_trig is
clk40: in std_logic;
rst40: in std_logic;
en: in std_logic;
mask: in std_logic(N_TRG - 1 downto 0);
mask: in std_logic_vector(N_TRG - 1 downto 0);
mark: in std_logic;
sctr: in std_logic_vector(47 downto 0);
rand: in std_logic_vector(31 downto 0);
......
components/solid/firmware/hdl/sc_timing.vhd
View file @ 241d34c7
......@@ -116,7 +116,7 @@ begin
sync_in_r <= sync_in when rising_edge(clk40_i); -- Should be IOB reg
trig_in_r <= trig_in when rising_edge(clk40_i); -- Should be IOB reg
trig_in_r_d <= trig_in_r when rising_dege(clk40_i);
trig_in_r_d <= trig_in_r when rising_edge(clk40_i);
process(clk40_i)
begin
......
components/solid/firmware/hdl/sc_trig.vhd
View file @ 241d34c7
......@@ -53,7 +53,7 @@ architecture rtl of sc_trig is
signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
signal ctrl: ipb_reg_v(0 downto 0);
signal ctrl, ctrl_mask: ipb_reg_v(0 downto 0);
signal stat: ipb_reg_v(1 downto 0);
signal stb: std_logic_vector(0 downto 0);
signal ctrl_dtmon_en, ctrl_trig_in_en, ctrl_trig_out_force: std_logic;
......@@ -68,6 +68,7 @@ architecture rtl of sc_trig is
signal b_go, t_go, b_valid, t_valid, b_blkend, t_blkend, blkend: std_logic;
signal tctr: std_logic_vector(27 downto 0);
signal ro_ctr: std_logic_vector(7 downto 0);
signal trig_in, trig_out: std_logic;
begin
......@@ -158,9 +159,11 @@ begin
reset => rst,
ipbus_in => ipbw(N_SLV_LOC_MASK),
ipbus_out => ipbr(N_SLV_LOC_MASK),
q => trig_mask,
q => ctrl_mask,
qmask(0) => (N_TRG - 1 downto 0 => '1', others => '0')
);
trig_mask <= ctrl_mask(0)(N_TRG - 1 downto 0);
ltrig: entity work.sc_local_trig
port map(
......@@ -315,6 +318,7 @@ begin
-- Ext trigger
trig_in <= ext_trig_in when rising_edge(clk40); -- Should be IOB reg
trig_out <= '0';
ext_trig_out <= trig_out or ctrl_trig_out_force when falling_edge(clk40); -- Should be IOB reg
end rtl;
components/solid/firmware/hdl/sc_trig_gen_or.vhd
View file @ 241d34c7
......@@ -61,7 +61,7 @@ begin
end if;
elsif m = '1' then
tc <= '0';
c <= (others => '0')
c <= (others => '0');
end if;
end if;
end process;
......
components/solid/firmware/hdl/sc_zs_sel.vhd
View file @ 241d34c7
......@@ -6,6 +6,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.top_decl.all;
......
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