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euro-adc-65m-14b-40cha-gw
Commit 44abe408 authored by Dave Newbold's avatar Dave Newbold
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Adding ZS thresh table; refactoring DAQ block

parent 082e6fad
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Showing with 152 additions and 87 deletions
components/solid/addr_table/sc_chan.xml
View file @ 44abe408
...@@ -20,16 +20,7 @@ ...@@ -20,16 +20,7 @@
<node id="addr" address="0x0"/> <node id="addr" address="0x0"/>
<node id="data" address="0x1" mode="port"/> <node id="data" address="0x1" mode="port"/>
</node> </node>
<node id="ptrs" address="0x4" description="buffer pointers" fwinfo="endpoint;width=1"> <node id="zs_thresh" address="0x4" mode="block" size="0x4" description="zero suppression thresholds" fwinfo="endpoint;width=2"/>
<node id="zs" address="0x0">
<node id="rw" mask="0xffff"/>
<node id="flags" mask="0xffff0000"/>
</node>
<node id="nzs" address="0x1">
<node id="r" mask="0xffff"/>
<node id="w" mask="0xffff0000"/>
</node>
</node>
<node id="trig_thresh" address="0x8" description="trigger thresholds" fwinfo="endpoint;width=2"> <node id="trig_thresh" address="0x8" description="trigger thresholds" fwinfo="endpoint;width=2">
<node id="threshold" address="0x0"> <node id="threshold" address="0x0">
<node id="thresh" mask="0x3ff"/> <node id="thresh" mask="0x3ff"/>
......
components/solid/addr_table/sc_daq.xml 0 → 100644
View file @ 44abe408
<node id="TOP">
<node id="chan" address="0x0" module="file://sc_chan.xml"/>
<node id="timing" address="0x10" module="file://sc_timing.xml"/>
<node id="fake" address="0x20" module="file://sc_fake.xml"/>
<node id="rtrig" address="0x28" fwinfo="endpoint;width=0"/>
<node id="tlink" address="0x30" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x40" module="file://sc_trig.xml"/>
<node id="roc" address="0x60" module="file://sc_roc.xml"/>
</node>
components/solid/firmware/cfg/sc_daq.dep
View file @ 44abe408
src sc_daq.vhd src sc_daq.vhd
src ipbus_decode_sc_daq.vhd
addrtab -t sc_daq.xml
src sc_rtrig.vhd
include sc_timing.dep sc_fake.dep sc_chan.dep sc_trig.dep sc_trig_link.dep sc_roc.dep include sc_timing.dep sc_fake.dep sc_chan.dep sc_trig.dep sc_trig_link.dep sc_roc.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
components/solid/firmware/cfg/sc_daq_sim.dep
View file @ 44abe408
src sc_daq.vhd src sc_daq.vhd
src ipbus_decode_sc_daq.vhd
addrtab -t sc_daq.xml
src sc_rtrig.vhd
include sc_timing_sim.dep sc_fake.dep sc_chan.dep sc_trig.dep sc_trig_link.dep sc_roc.dep include sc_timing_sim.dep sc_fake.dep sc_chan.dep sc_trig.dep sc_trig_link.dep sc_roc.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
components/solid/firmware/cfg/sc_trig.dep
View file @ 44abe408
...@@ -5,3 +5,4 @@ src ipbus_decode_sc_trig.vhd ...@@ -5,3 +5,4 @@ src ipbus_decode_sc_trig.vhd
addrtab -t sc_trig.xml addrtab -t sc_trig.xml
include -c ipbus-firmware:components/ipbus_slaves syncreg_v.dep include -c ipbus-firmware:components/ipbus_slaves syncreg_v.dep
src -c ipbus-firmware:components/ipbus_slaves ipbus_reg_types.vhd src -c ipbus-firmware:components/ipbus_slaves ipbus_reg_types.vhd
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
components/solid/firmware/hdl/sc_chan.vhd
View file @ 44abe408
...@@ -39,6 +39,7 @@ entity sc_chan is ...@@ -39,6 +39,7 @@ entity sc_chan is
d_test: in std_logic_vector(13 downto 0); d_test: in std_logic_vector(13 downto 0);
q_test: out std_logic_vector(13 downto 0); q_test: out std_logic_vector(13 downto 0);
sync_ctrl: in std_logic_vector(3 downto 0); sync_ctrl: in std_logic_vector(3 downto 0);
zs_sel: in std_logic_vector(1 downto 0);
sctr: in std_logic_vector(47 downto 0); sctr: in std_logic_vector(47 downto 0);
fake: in std_logic_vector(13 downto 0); fake: in std_logic_vector(13 downto 0);
nzs_en: in std_logic; nzs_en: in std_logic;
...@@ -70,6 +71,9 @@ architecture rtl of sc_chan is ...@@ -70,6 +71,9 @@ architecture rtl of sc_chan is
signal ctrl_en_sync, ctrl_en_buf, ctrl_invert: std_logic; signal ctrl_en_sync, ctrl_en_buf, ctrl_invert: std_logic;
signal ctrl_mode, ctrl_src: std_logic_vector(1 downto 0); signal ctrl_mode, ctrl_src: std_logic_vector(1 downto 0);
signal cap_full, buf_full, dr_full, dr_warn: std_logic; signal cap_full, buf_full, dr_full, dr_warn: std_logic;
signal zs_thresh_v: ipb_reg_v(N_ZS_THRESH - 1 downto 0);
signal zs_sel: integer range 2 ** zs_sel'length - 1 downto 0 := 0;
signal zs_thresh: std_logic_vector(13 downto 0);
signal sctr_p: std_logic_vector(11 downto 0); signal sctr_p: std_logic_vector(11 downto 0);
signal dr_d: std_logic_vector(31 downto 0); signal dr_d: std_logic_vector(31 downto 0);
signal ro_en, keep_i, flush_i, err_i, req, blkend, dr_blkend, dr_wen: std_logic; signal ro_en, keep_i, flush_i, err_i, req, blkend, dr_blkend, dr_wen: std_logic;
...@@ -161,6 +165,24 @@ begin ...@@ -161,6 +165,24 @@ begin
flush_i <= flush and ro_en; flush_i <= flush and ro_en;
veto <= dr_warn or not ro_en; veto <= dr_warn or not ro_en;
-- ZS thresholds
zs_thresh: entity work.ipbus_reg_v
generic map(
N_REG => N_ZS_THRESH
)
port map(
clk => clk,
reset => rst,
ipbus_in => ipbw(N_SLV_ZS_THRESH),
ipbus_out => ipbr(N_SLV_ZS_THRESH),
q => zs_thresh_v,
qmask => (others => X"00003fff")
);
zs_sel_i <= to_integer(unsigned(zs_sel));
zs_thresh <= zs_thresh_v(zs_sel_i)(13 downto 0) when zs_sel_i < N_SZ_THRESH else (others => '0');
-- Buffers -- Buffers
blkend <= and_reduce(sctr(BLK_RADIX - 1 downto 0)); blkend <= and_reduce(sctr(BLK_RADIX - 1 downto 0));
...@@ -171,8 +193,6 @@ begin ...@@ -171,8 +193,6 @@ begin
rst => rst, rst => rst,
ipb_in => ipbw(N_SLV_BUF), ipb_in => ipbw(N_SLV_BUF),
ipb_out => ipbr(N_SLV_BUF), ipb_out => ipbr(N_SLV_BUF),
ipb_in_ptr => ipbw(N_SLV_PTRS),
ipb_out_ptr => ipbr(N_SLV_PTRS),
mode => ctrl_mode, mode => ctrl_mode,
clk40 => clk40, clk40 => clk40,
clk160 => clk160, clk160 => clk160,
...@@ -181,7 +201,7 @@ begin ...@@ -181,7 +201,7 @@ begin
blkend => blkend, blkend => blkend,
nzs_en => nzs_en, nzs_en => nzs_en,
cap_full => cap_full, cap_full => cap_full,
zs_thresh => ctrl(0)(29 downto 16), -- CDC zs_thresh => zs_thresh,
q_test => q_test, q_test => q_test,
zs_en => zs_en, zs_en => zs_en,
buf_full => buf_full, buf_full => buf_full,
......
components/solid/firmware/hdl/sc_chan_buf.vhd
View file @ 44abe408
...@@ -19,8 +19,6 @@ entity sc_chan_buf is ...@@ -19,8 +19,6 @@ entity sc_chan_buf is
rst: in std_logic; rst: in std_logic;
ipb_in: in ipb_wbus; -- clk dom ipb_in: in ipb_wbus; -- clk dom
ipb_out: out ipb_rbus; -- clk dom ipb_out: out ipb_rbus; -- clk dom
ipb_in_ptr: in ipb_wbus; -- clk dom
ipb_out_ptr: out ipb_rbus; -- clk dom
mode: in std_logic_vector(1 downto 0); -- buffer counter mode; clk dom mode: in std_logic_vector(1 downto 0); -- buffer counter mode; clk dom
clk40: in std_logic; clk40: in std_logic;
clk160: in std_logic; clk160: in std_logic;
...@@ -44,8 +42,8 @@ end sc_chan_buf; ...@@ -44,8 +42,8 @@ end sc_chan_buf;
architecture rtl of sc_chan_buf is architecture rtl of sc_chan_buf is
constant NZS_LAST_ADDR: integer := NZS_BLKS * 2 ** BLK_RADIX - 1; constant NZS_LAST_ADDR: integer := NZS_BLKS * 2 ** BLK_RADIX + ZS_DEL - 1;
constant ZS_FIRST_ADDR: integer := NZS_BLKS * 2 ** BLK_RADIX; constant ZS_FIRST_ADDR: integer := NZS_BLKS * 2 ** BLK_RADIX + ZS_DEL;
constant ZS_LAST_ADDR: integer := 2 ** BUF_RADIX - 1; constant ZS_LAST_ADDR: integer := 2 ** BUF_RADIX - 1;
signal norm_mode, pb_mode, cap_mode: std_logic; signal norm_mode, pb_mode, cap_mode: std_logic;
...@@ -109,13 +107,6 @@ begin ...@@ -109,13 +107,6 @@ begin
wenz when "11", wenz when "11",
wez when "01", wez when "01",
'0' when others; '0' when others;
-- Pointer access
ipb_out_ptr.ipb_rdata <= X"0000" & (15 - BUF_RADIX downto 0 => '0') & std_logic_vector(pnz) when ipb_in_ptr.ipb_addr(0) = '0' else
(15 - BUF_RADIX downto 0 => '0') & std_logic_vector(pzw) & (15 - BUF_RADIX downto 0 => '0') & std_logic_vector(pzr);
ipb_out_ptr.ipb_ack <= ipb_in_ptr.ipb_strobe;
ipb_out_ptr.ipb_err <= '0';
-- NZS pointer control -- NZS pointer control
......
components/solid/firmware/hdl/sc_chan_trig.vhd
View file @ 44abe408
...@@ -55,7 +55,7 @@ begin ...@@ -55,7 +55,7 @@ begin
); );
dd <= d when rising_edge(clk40); -- pipeline register dd <= d when rising_edge(clk40); -- pipeline register
trg0: entity work.sc_ctrig_thresh -- direct threshold trigger, delay = 1 trg0: entity work.sc_ctrig_thresh -- direct threshold trigger, delay = 1
generic map( generic map(
VAL_WIDTH => VAL_WIDTH, VAL_WIDTH => VAL_WIDTH,
......
components/solid/firmware/hdl/sc_channels.vhd
View file @ 44abe408
...@@ -30,6 +30,7 @@ entity sc_channels is ...@@ -30,6 +30,7 @@ entity sc_channels is
d_p: in std_logic_vector(N_CHAN - 1 downto 0); d_p: in std_logic_vector(N_CHAN - 1 downto 0);
d_n: in std_logic_vector(N_CHAN - 1 downto 0); d_n: in std_logic_vector(N_CHAN - 1 downto 0);
sync_ctrl: in std_logic_vector(3 downto 0); sync_ctrl: in std_logic_vector(3 downto 0);
zs_sel: in std_logic_vector(1 downto 0);
sctr: in std_logic_vector(47 downto 0); sctr: in std_logic_vector(47 downto 0);
fake: in std_logic_vector(13 downto 0); fake: in std_logic_vector(13 downto 0);
nzs_en: in std_logic; nzs_en: in std_logic;
...@@ -110,6 +111,7 @@ begin ...@@ -110,6 +111,7 @@ begin
d_test => q_test(p), d_test => q_test(p),
q_test => q_test(i), q_test => q_test(i),
sync_ctrl => sync_ctrl, sync_ctrl => sync_ctrl,
zs_sel => zs_sel,
sctr => sctr, sctr => sctr,
fake => fake, fake => fake,
nzs_en => nzs_en, nzs_en => nzs_en,
......
components/solid/firmware/hdl/sc_daq.vhd
View file @ 44abe408
...@@ -8,6 +8,7 @@ library IEEE; ...@@ -8,6 +8,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all; use work.ipbus.all;
use work.ipbus_decode_sc_daq.all;
use work.top_decl.all; use work.top_decl.all;
...@@ -15,18 +16,8 @@ entity sc_daq is ...@@ -15,18 +16,8 @@ entity sc_daq is
port( port(
ipb_clk: in std_logic; ipb_clk: in std_logic;
ipb_rst: in std_logic; ipb_rst: in std_logic;
ipb_in_timing: in ipb_wbus; ipb_in: in ipb_wbus;
ipb_out_timing: out ipb_rbus; ipb_out: out ipb_rbus;
ipb_in_fake: in ipb_wbus;
ipb_out_fake: out ipb_rbus;
ipb_in_chan: in ipb_wbus;
ipb_out_chan: out ipb_rbus;
ipb_in_trig: in ipb_wbus;
ipb_out_trig: out ipb_rbus;
ipb_in_tlink: in ipb_wbus;
ipb_out_tlink: out ipb_rbus;
ipb_in_roc: in ipb_wbus;
ipb_out_roc: out ipb_rbus;
rst_mmcm: in std_logic; rst_mmcm: in std_logic;
locked: out std_logic; locked: out std_logic;
clk_in_p: in std_logic; clk_in_p: in std_logic;
...@@ -48,12 +39,16 @@ end sc_daq; ...@@ -48,12 +39,16 @@ end sc_daq;
architecture rtl of sc_daq is architecture rtl of sc_daq is
signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
signal clk40_i, rst40_i, clk160, clk280: std_logic; signal clk40_i, rst40_i, clk160, clk280: std_logic;
signal sync_ctrl: std_logic_vector(3 downto 0); signal sync_ctrl: std_logic_vector(3 downto 0);
signal sctr: std_logic_vector(47 downto 0); signal sctr: std_logic_vector(47 downto 0);
signal trig_en, nzs_en, zs_en: std_logic; signal trig_en, nzs_en, zs_en: std_logic;
signal trig_keep, trig_flush, trig_veto: std_logic_vector(N_CHAN - 1 downto 0); signal trig_keep, trig_flush, trig_veto: std_logic_vector(N_CHAN - 1 downto 0);
signal fake: std_logic_vector(13 downto 0); signal fake: std_logic_vector(13 downto 0);
signal force_trig: std_logic;
signal zs_sel: std_logic_vector(1 downto 0);
signal chan_trig: sc_trig_array; signal chan_trig: sc_trig_array;
signal link_d, link_q: std_logic_vector(15 downto 0); signal link_d, link_q: std_logic_vector(15 downto 0);
signal link_d_valid, link_q_valid, link_ack: std_logic; signal link_d_valid, link_q_valid, link_ack: std_logic;
...@@ -64,14 +59,29 @@ architecture rtl of sc_daq is ...@@ -64,14 +59,29 @@ architecture rtl of sc_daq is
begin begin
-- ipbus address decode
fabric: entity work.ipbus_fabric_sel
generic map(
NSLV => N_SLAVES,
SEL_WIDTH => IPBUS_SEL_WIDTH
)
port map(
ipb_in => ipb_in,
ipb_out => ipb_out,
sel => ipbus_sel_sc_daq(ipb_in.ipb_addr),
ipb_to_slaves => ipbw,
ipb_from_slaves => ipbr
);
-- Timing -- Timing
timing: entity work.sc_timing timing: entity work.sc_timing
port map( port map(
clk => ipb_clk, clk => ipb_clk,
rst => ipb_rst, rst => ipb_rst,
ipb_in => ipb_in_timing, ipb_in => ipbw(N_SLV_TIMING),
ipb_out => ipb_out_timing, ipb_out => ipbr(N_SLV_TIMING),
rst_mmcm => rst_mmcm, rst_mmcm => rst_mmcm,
locked => locked, locked => locked,
clk_in_p => clk_in_p, clk_in_p => clk_in_p,
...@@ -99,14 +109,30 @@ begin ...@@ -99,14 +109,30 @@ begin
port map( port map(
clk => ipb_clk, clk => ipb_clk,
rst => ipb_rst, rst => ipb_rst,
ipb_in => ipb_in_fake, ipb_in => ipbw(N_SLV_FAKE),
ipb_out => ipb_out_fake, ipb_out => ipbr(N_SLV_FAKE),
clk40 => clk40_i, clk40 => clk40_i,
rst40 => rst40_i, rst40 => rst40_i,
rand => rand, rand => rand,
sctr => sctr(7 downto 0), sctr => sctr(7 downto 0),
fake => fake fake => fake
); );
-- External / random trigger generator
rtrig: entity work.sc_rtrig
port map(
clk => ipb_clk,
rst => ipb_rst,
ipb_in => ipbw(N_SLV_RTRIG),
ipb_out => ipbr(N_SLV_RTRIG),
clk40 => clk40_i,
rst40 => rst40_i,
rand => rand,
sctr => sctr,
trig => force_trig,
trig_in => trig_in
);
-- Data channels -- Data channels
...@@ -114,8 +140,8 @@ begin ...@@ -114,8 +140,8 @@ begin
port map( port map(
clk => ipb_clk, clk => ipb_clk,
rst => ipb_rst, rst => ipb_rst,
ipb_in => ipb_in_chan, ipb_in => ipbw(N_SLV_CHAN),
ipb_out => ipb_out_chan, ipb_out => ipbr(N_SLV_CHAN),
chan => chan, chan => chan,
clk40 => clk40_i, clk40 => clk40_i,
rst40 => rst40_i, rst40 => rst40_i,
...@@ -124,6 +150,7 @@ begin ...@@ -124,6 +150,7 @@ begin
d_p => d_p, d_p => d_p,
d_n => d_n, d_n => d_n,
sync_ctrl => sync_ctrl, sync_ctrl => sync_ctrl,
zs_sel => zs_sel,
sctr => sctr, sctr => sctr,
fake => fake, fake => fake,
nzs_en => nzs_en, nzs_en => nzs_en,
...@@ -147,8 +174,8 @@ begin ...@@ -147,8 +174,8 @@ begin
port map( port map(
clk => ipb_clk, clk => ipb_clk,
rst => ipb_rst, rst => ipb_rst,
ipb_in => ipb_in_trig, ipb_in => ipbw(N_SLV_TRIG),
ipb_out => ipb_out_trig, ipb_out => ipbr(N_SLV_TRIG),
clk40 => clk40_i, clk40 => clk40_i,
rst40 => rst40_i, rst40 => rst40_i,
clk160 => clk160, clk160 => clk160,
...@@ -159,7 +186,9 @@ begin ...@@ -159,7 +186,9 @@ begin
keep => trig_keep, keep => trig_keep,
flush => trig_flush, flush => trig_flush,
veto => trig_veto, veto => trig_veto,
zs_sel => zs_sel,
trig => chan_trig, trig => chan_trig,
force => force_trig,
ro_d => trig_d, ro_d => trig_d,
ro_blkend => trig_blkend, ro_blkend => trig_blkend,
ro_we => trig_we, ro_we => trig_we,
...@@ -177,8 +206,8 @@ begin ...@@ -177,8 +206,8 @@ begin
port map( port map(
clk => ipb_clk, clk => ipb_clk,
rst => ipb_rst, rst => ipb_rst,
ipb_in => ipb_in_tlink, ipb_in => ipbw(N_SLV_TLINK),
ipb_out => ipb_out_tlink, ipb_out => ipbr(N_SLV_TLINK),
clk125 => clk125, clk125 => clk125,
rst125 => rst125, rst125 => rst125,
clk40 => clk40_i, clk40 => clk40_i,
...@@ -196,8 +225,8 @@ begin ...@@ -196,8 +225,8 @@ begin
port map( port map(
clk => ipb_clk, clk => ipb_clk,
rst => ipb_rst, rst => ipb_rst,
ipb_in => ipb_in_roc, ipb_in => ipbw(N_SLV_ROC),
ipb_out => ipb_out_roc, ipb_out => ipbr(N_SLV_ROC),
board_id => board_id, board_id => board_id,
clk40 => clk40_i, clk40 => clk40_i,
rst40 => rst40_i, rst40 => rst40_i,
......
components/solid/firmware/hdl/sc_rtrig.vhd 0 → 100644
View file @ 44abe408
-- sc_rtrig
--
-- Random and external trigger generator
--
-- Dave Newbold, August 2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
entity sc_rtrig is
port(
clk: in std_logic; -- ipbus clock (nominally ~30MHz) & reset
rst: in std_logic;
ipb_in: in ipb_wbus;
ipb_out: out ipb_rbus;
clk40: in std_logic;
rst40: in std_logic;
rand: in std_logic_vector(31 downto 0);
sctr: in std_logic_vector(47 downto 0);
trig: out std_logic;
trig_in: in std_logic
);
end sc_rtrig;
architecture rtl of sc_rtrig is
begin
ipb_out <= IPB_RBUS_NULL;
trig <= '0';
end rtl;
components/solid/firmware/hdl/sc_trig.vhd
View file @ 44abe408
...@@ -31,6 +31,7 @@ entity sc_trig is ...@@ -31,6 +31,7 @@ entity sc_trig is
keep: out std_logic_vector(N_CHAN - 1 downto 0); keep: out std_logic_vector(N_CHAN - 1 downto 0);
flush: out std_logic_vector(N_CHAN - 1 downto 0); flush: out std_logic_vector(N_CHAN - 1 downto 0);
veto: in std_logic_vector(N_CHAN - 1 downto 0); veto: in std_logic_vector(N_CHAN - 1 downto 0);
zs_sel: out std_logic_vector(1 downto 0);
trig: in sc_trig_array; trig: in sc_trig_array;
ro_d: out std_logic_vector(31 downto 0); ro_d: out std_logic_vector(31 downto 0);
ro_blkend: out std_logic; ro_blkend: out std_logic;
...@@ -164,7 +165,11 @@ begin ...@@ -164,7 +165,11 @@ begin
); );
q <= lq; q <= lq;
q_valid <= lvalid; q_valid <= lvalid;
-- ZS threshold select
zs_sel <= "00";
-- Readout sequencer -- Readout sequencer
......
projects/64ch/addr_table/top.xml
View file @ 44abe408
<node id="TOP"> <node id="TOP">
<node id="csr" address="0x0" module="file://payload.xml"/> <node id="csr" address="0x0" module="file://payload.xml"/>
<node id="chan" address="0x10" module="file://sc_chan.xml"/>
<node id="io" address="0x20" module="file://sc_io_64chan.xml"/> <node id="io" address="0x20" module="file://sc_io_64chan.xml"/>
<node id="timing" address="0x40" module="file://sc_timing.xml"/> <node id="daq" address="0x100" module="file://sc_daq.xml"/>
<node id="fake" address="0x50" module="file://sc_fake.xml"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x80" module="file://sc_trig.xml"/>
<node id="roc" address="0xa0" module="file://sc_roc.xml"/>
</node> </node>
projects/64ch/addr_table/top_sim.xml
View file @ 44abe408
<node id="TOP"> <node id="TOP">
<node id="csr" address="0x0" module="file://payload.xml"/> <node id="csr" address="0x0" module="file://payload.xml"/>
<node id="chan" address="0x8" module="file://sc_chan.xml"/> <node id="daq" address="0x100" module="file://sc_daq.xml"/>
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="fake" address="0x50" module="file://sc_fake.xml"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x80" module="file://sc_trig.xml"/>
<node id="roc" address="0xa0" module="file://sc_roc.xml"/>
</node> </node>
projects/64ch/firmware/hdl/top_decl.vhd
View file @ 44abe408
...@@ -19,7 +19,9 @@ package top_decl is ...@@ -19,7 +19,9 @@ package top_decl is
constant BUF_RADIX: integer := 11; -- One BRAM for NZS / ZS buffer constant BUF_RADIX: integer := 11; -- One BRAM for NZS / ZS buffer
constant NZS_BLKS: integer := 2; -- Reserve two blocks of space for NZS buffer constant NZS_BLKS: integer := 2; -- Reserve two blocks of space for NZS buffer
constant ZS_BLKS: integer := 2; -- Time window for ZS buffer constant ZS_BLKS: integer := 2; -- Time window for ZS buffer
constant ZS_DEL: integer := 0; -- Additional samples to form channel trigger
constant N_TRG: integer := 4; -- Number of trigger types constant N_TRG: integer := 4; -- Number of trigger types
constant N_ZS_THRESH: integer := 4; -- Number of ZS thresholds
constant N_CHAN_TRG: integer := 3; -- Number of channel trigger bits constant N_CHAN_TRG: integer := 3; -- Number of channel trigger bits
constant FIFO_RADIX: integer := 3; -- 8 FIFO blocks in readout buffer constant FIFO_RADIX: integer := 3; -- 8 FIFO blocks in readout buffer
......
projects/8ch/addr_table/top.xml
View file @ 44abe408
<node id="TOP"> <node id="TOP">
<node id="csr" address="0x0" module="file://payload.xml"/> <node id="csr" address="0x0" module="file://payload.xml"/>
<node id="chan" address="0x10" module="file://sc_chan.xml"/>
<node id="io" address="0x20" module="file://sc_io.xml"/> <node id="io" address="0x20" module="file://sc_io.xml"/>
<node id="timing" address="0x40" module="file://sc_timing.xml"/> <!-- <node id="mon" address="0x40" module="file://sc_temp.xml"/> -->
<node id="fake" address="0x50" module="file://sc_fake.xml"/> <node id="daq" address="0x100" module="file://sc_daq.xml"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x80" module="file://sc_trig.xml"/>
<node id="roc" address="0xa0" module="file://sc_roc.xml"/>
<!-- <node id="mon" address="0x90" module="file://sc_temp.xml"/> -->
</node> </node>
projects/8ch/addr_table/top_sim.xml
View file @ 44abe408
<node id="TOP"> <node id="TOP">
<node id="csr" address="0x0" module="file://payload.xml"/> <node id="csr" address="0x0" module="file://payload.xml"/>
<node id="chan" address="0x10" module="file://sc_chan.xml"/> <node id="daq" address="0x100" module="file://sc_daq.xml"/>
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="fake" address="0x50" module="file://sc_fake.xml"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x80" module="file://sc_trig.xml"/>
<node id="roc" address="0xa0" module="file://sc_roc.xml"/>
</node> </node>
projects/8ch/firmware/hdl/payload.vhd
View file @ 44abe408
...@@ -164,18 +164,8 @@ begin ...@@ -164,18 +164,8 @@ begin
port map( port map(
ipb_clk => ipb_clk, ipb_clk => ipb_clk,
ipb_rst => ipb_rst, ipb_rst => ipb_rst,
ipb_in_timing => ipbw(N_SLV_TIMING), ipb_in => ipbw(N_SLV_DAQ),
ipb_out_timing => ipbr(N_SLV_TIMING), ipb_out => ipbr(N_SLV_DAQ),
ipb_in_fake => ipbw(N_SLV_FAKE),
ipb_out_fake => ipbr(N_SLV_FAKE),
ipb_in_chan => ipbw(N_SLV_CHAN),
ipb_out_chan => ipbr(N_SLV_CHAN),
ipb_in_trig => ipbw(N_SLV_TRIG),
ipb_out_trig => ipbr(N_SLV_TRIG),
ipb_in_tlink => ipbw(N_SLV_TLINK),
ipb_out_tlink => ipbr(N_SLV_TLINK),
ipb_in_roc => ipbw(N_SLV_ROC),
ipb_out_roc => ipbr(N_SLV_ROC),
rst_mmcm => ctrl_rst_mmcm, rst_mmcm => ctrl_rst_mmcm,
locked => locked, locked => locked,
clk_in_p => clk40_p, clk_in_p => clk40_p,
......
projects/8ch/firmware/hdl/top_decl.vhd
View file @ 44abe408
...@@ -19,7 +19,9 @@ package top_decl is ...@@ -19,7 +19,9 @@ package top_decl is
constant BUF_RADIX: integer := 11; -- One BRAM for NZS / ZS buffer constant BUF_RADIX: integer := 11; -- One BRAM for NZS / ZS buffer
constant NZS_BLKS: integer := 2; -- Reserve two blocks of space for NZS buffer constant NZS_BLKS: integer := 2; -- Reserve two blocks of space for NZS buffer
constant ZS_BLKS: integer := 2; -- Time window for ZS buffer constant ZS_BLKS: integer := 2; -- Time window for ZS buffer
constant ZS_DEL: integer := 0; -- Additional samples to form channel trigger
constant N_TRG: integer := 4; -- Number of trigger types constant N_TRG: integer := 4; -- Number of trigger types
constant N_ZS_THRESH: integer := 4; -- Number of ZS thresholds
constant N_CHAN_TRG: integer := 3; -- Number of channel trigger bits constant N_CHAN_TRG: integer := 3; -- Number of channel trigger bits
constant FIFO_RADIX: integer := 3; -- 8 FIFO blocks in readout buffer constant FIFO_RADIX: integer := 3; -- 8 FIFO blocks in readout buffer
......
projects/8ch/firmware/sim_hdl/top_decl.vhd
View file @ 44abe408
...@@ -19,7 +19,9 @@ package top_decl is ...@@ -19,7 +19,9 @@ package top_decl is
constant BUF_RADIX: integer := 11; -- One BRAM for NZS / ZS buffer constant BUF_RADIX: integer := 11; -- One BRAM for NZS / ZS buffer
constant NZS_BLKS: integer := 2; -- Reserve two blocks of space for NZS buffer constant NZS_BLKS: integer := 2; -- Reserve two blocks of space for NZS buffer
constant ZS_BLKS: integer := 2; -- Time window for ZS buffer constant ZS_BLKS: integer := 2; -- Time window for ZS buffer
constant ZS_DEL: integer := 0; -- Additional samples to form channel trigger
constant N_TRG: integer := 4; -- Number of trigger types constant N_TRG: integer := 4; -- Number of trigger types
constant N_ZS_THRESH: integer := 4; -- Number of ZS thresholds
constant N_CHAN_TRG: integer := 3; -- Number of channel trigger bits constant N_CHAN_TRG: integer := 3; -- Number of channel trigger bits
constant FIFO_RADIX: integer := 3; -- 8 FIFO blocks in readout buffer constant FIFO_RADIX: integer := 3; -- 8 FIFO blocks in readout buffer
......
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