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euro-adc-65m-14b-40cha-gw
Commit 3e1001d1 authored by Dave Newbold's avatar Dave Newbold
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Fixing clock sync issue; removing ZS_DELAY

parent 071a848e
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Showing with 25 additions and 33 deletions
components/solid/addr_table/sc_timing.xml
View file @ 3e1001d1
......@@ -16,8 +16,6 @@
<node id="stat" address="0x8">
<node id="wait_sync" mask="0x1"/>
<node id="sync_err" mask="0x2"/>
<node id="io_err" mask="0x4"/>
<node id="locked" mask="0x8"/>
</node>
<node id="sctr_l" address="0x9"/>
<node id="sctr_h" address="0xa"/>
......
components/solid/firmware/hdl/sc_chan.vhd
View file @ 3e1001d1
......@@ -173,7 +173,7 @@ begin
qmask => (others => X"00003fff")
);
zs_sel_i <= to_integer(unsigned(zs_sel));
zs_sel_i <= to_integer(unsigned(zs_sel)); -- Might need pipelining here
zs_thresh <= zs_thresh_v(zs_sel_i)(13 downto 0) when zs_sel_i < N_ZS_THRESH else (others => '0');
-- Buffers
......
components/solid/firmware/hdl/sc_chan_buf.vhd
View file @ 3e1001d1
......@@ -44,8 +44,8 @@ end sc_chan_buf;
architecture rtl of sc_chan_buf is
constant NZS_LAST_ADDR: integer := NZS_BLKS * 2 ** BLK_RADIX + ZS_DEL - 1;
constant ZS_FIRST_ADDR: integer := NZS_BLKS * 2 ** BLK_RADIX + ZS_DEL;
constant NZS_LAST_ADDR: integer := NZS_BLKS * 2 ** BLK_RADIX - 1;
constant ZS_FIRST_ADDR: integer := NZS_BLKS * 2 ** BLK_RADIX;
constant ZS_LAST_ADDR: integer := 2 ** BUF_RADIX - 1;
signal c: unsigned(1 downto 0);
......
components/solid/firmware/hdl/sc_timing.vhd
View file @ 3e1001d1
......@@ -51,9 +51,12 @@ architecture rtl of sc_timing is
signal rst_ctr: unsigned(3 downto 0);
signal ctrl_rst_ctr, ctrl_cap_ctr, ctrl_en_sync, ctrl_force_sync, ctrl_pipeline_en, ctrl_send_sync: std_logic;
signal ctrl_chan_slip, ctrl_chan_rst_buf, ctrl_chan_cap, ctrl_chan_inc: std_logic;
signal frst, sync, sync_f, wait_sync, sync_err, io_err: std_logic;
signal frst, sync, wait_sync, sync_err, io_err: std_logic;
signal sync_in_r, trig_in_r, trig_in_r_d: std_logic;
signal sync_ctr, trig_ctr: unsigned(31 downto 0);
attribute IOB: string;
attribute IOB of sync_in_r, trig_in_r: signal is "TRUE";
begin
......@@ -107,7 +110,7 @@ begin
ctrl_chan_rst_buf <= ctrl(0)(13);
ctrl_chan_cap <= ctrl(0)(14);
ctrl_chan_inc <= ctrl(0)(15);
stat(0) <= X"0000000" & '0' & io_err & sync_err & wait_sync;
stat(0) <= X"0000000" & "00" & sync_err & wait_sync;
stat(1) <= std_logic_vector(sctr_s(31 downto 0));
stat(2) <= X"0000" & std_logic_vector(sctr_s(47 downto 32));
stat(3) <= std_logic_vector(sync_ctr);
......@@ -139,7 +142,6 @@ begin
-- Sync signals
sync <= (sync_in_r and ctrl_en_sync) or (ctrl_force_sync and stb(0));
sync_f <= sync and wait_sync;
process(clk40_i)
begin
......@@ -158,7 +160,6 @@ begin
end if;
end process;
io_err <= '1';
led <= not (wait_sync or sync_err);
-- Sample counter
......@@ -166,7 +167,7 @@ begin
process(clk40_i)
begin
if rising_edge(clk40_i) then
if rst40_i = '1' or sync_f = '1' then
if rst40_i = '1' or wait_sync = '1' then
sctr_i <= X"000000000001";
else
sctr_i <= sctr_i + 1;
......@@ -195,7 +196,7 @@ begin
clk40 => clk40_i,
rst40 => rst40_i,
en => ctrl_pipeline_en,
sync => sync_f,
sync => sync,
sctr => sctr_i,
nzs_en => nzs_en,
zs_en => zs_en,
......
components/solid/firmware/hdl/sc_timing_startup.vhd
View file @ 3e1001d1
......@@ -44,21 +44,14 @@ begin
up <= '1';
end if;
if up = '1' then
-- if and_reduce(std_logic_vector(sctr(BLK_RADIX - 1 downto 0))) = '1' then
-- if unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = 8 then
-- nzs_en <= '1';
-- elsif unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = 8 + NZS_BLKS then
-- zs_en <= '1';
-- elsif unsigned(sctr(7 + BLK_RADIX downto BLK_RADIX)) = 7 + NZS_BLKS + ZS_BLKS then
-- trig_en <= '1';
-- end if;
-- end if;
if unsigned(sctr(7 + BLK_RADIX downto 0)) = 9 * 2 ** BLK_RADIX - 1 then
nzs_en <= '1';
elsif unsigned(sctr(7 + BLK_RADIX downto 0)) = (9 + NZS_BLKS) * 2 ** BLK_RADIX + ZS_DEL - 2 then
zs_en <= '1';
elsif unsigned(sctr(7 + BLK_RADIX downto 0)) = (10 + NZS_BLKS + ZS_BLKS) * 2 ** BLK_RADIX then
trig_en <= '1';
if and_reduce(std_logic_vector(sctr(BLK_RADIX - 1 downto 0))) = '1' then
if unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = 0 then
nzs_en <= '1';
elsif unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = NZS_BLKS then
zs_en <= '1';
elsif unsigned(sctr(7 + BLK_RADIX downto BLK_RADIX)) = NZS_BLKS + ZS_BLKS - 1 then
trig_en <= '1';
end if;
end if;
end if;
end if;
......
components/solid/firmware/hdl/sc_zs_sel.vhd
View file @ 3e1001d1
......@@ -25,24 +25,25 @@ end sc_zs_sel;
architecture rtl of sc_zs_sel is
signal mark_del: std_logic_vector(ZS_DEL - 1 downto 0);
signal m: std_logic;
-- signal mark_del: std_logic_vector(ZS_DEL - 1 downto 0);
-- signal m: std_logic;
signal sel_i: std_logic_vector(1 downto 0);
signal ti: integer range 15 downto 0 := 0;
signal zs: std_logic_vector(1 downto 0);
begin
mark_del <= mark_del(ZS_DEL - 2 downto 0) & mark when rising_edge(clk40);
m <= mark_del(ZS_DEL - 1);
-- mark_del <= mark_del(ZS_DEL - 2 downto 0) & mark when rising_edge(clk40);
-- m <= mark_del(ZS_DEL - 1);
ti <= to_integer(unsigned(trig(3 downto 0)));
zs <= zscfg(ti * 2 + 1 downto ti * 2);
process(clk40)
begin
if rising_edge(clk40) then
if rst40 = '1' or m = '1' then
-- if rst40 = '1' or m = '1' then
if rst40 = '1' or mark = '1' then
sel_i <= "00";
sel <= sel_i;
elsif trig_valid = '1' and unsigned(zs) > unsigned(sel_i) then
......
projects/8ch/firmware/sim_hdl/top_decl.vhd
View file @ 3e1001d1
......@@ -20,7 +20,6 @@ package top_decl is
constant BUF_RADIX: integer := 11; -- One BRAM for NZS / ZS buffer
constant NZS_BLKS: integer := 2; -- Reserve two blocks of space for NZS buffer
constant ZS_BLKS: integer := 2; -- Time window for ZS buffer
constant ZS_DEL: integer := 8; -- Additional samples to form channel trigger
constant N_TRG: integer := 4; -- Number of trigger types
constant N_ZS_THRESH: integer := 4; -- Number of ZS thresholds
constant N_CHAN_TRG: integer := 3; -- Number of channel trigger bits
......
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