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euro-adc-65m-14b-40cha-gw
Commit 3c50d807 authored by Dave Newbold's avatar Dave Newbold
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Address table fix; ID register fix

parent a1628f5b
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components/solid/addr_table/sc_seq.xml
View file @ 3c50d807
<node id="seq" address="0x8" description="readout sequencer" fwinfo="endpoint">
<node id="seq" description="readout sequencer" fwinfo="endpoint">
<node id="buf" address="0x0" description="sequence buffer" fwinfo="endpoint;width=1">
<node id="addr" address="0x0"/>
<node id="data" address="0x1" mode="port"/>
......
projects/64ch/firmware/hdl/payload.vhd
View file @ 3c50d807
......@@ -98,7 +98,7 @@ begin
);
stat(0) <= X"a753" & FW_REV;
stat(1) <= X"00000" & addr & '0' & chan_err & idelayctrl_rdy & locked;
stat(1) <= X"0000" & addr & "00000" & chan_err & idelayctrl_rdy & locked;
soft_rst <= ctrl(0)(0);
nuke <= ctrl(0)(1);
......
projects/64ch/software/ro_test.py
View file @ 3c50d807
......@@ -46,7 +46,7 @@ for i in range(1):
board.getNode("daq.chan.csr.ctrl.mode").write(0x0) # Set to normal DAQ mode
board.getNode("daq.chan.csr.ctrl.src").write(0x3) # Set source to fake data
board.getNode("daq.chan.zs_thresh").writeBlock([0x0, 0x1]) # Set ZS thresholds #0 = 0, #1 =1
board.getNode("daq.chan.trig_thresh.threshold.thresh").write(0x1000) # Set ctrig 0 threshold
board.getNode("daq.chan.trig_thresh.threshold.thresh").write(0x1000) # Set ctrig 0 threshold
board.getNode("daq.chan.csr.ctrl.en_buf").write(0x1) # Enable this channel
board.getNode("daq.fake.ctrl.mode").write(0x1) # Set fake data to pulse
......
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