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Commit 2680a008 authored by Dave Newbold's avatar Dave Newbold
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Adding new neutron trigger implementation

parent cdf79352
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Showing with 372 additions and 42 deletions
components/solid/addr_table/sc_chan.xml
View file @ 2680a008
......@@ -31,8 +31,18 @@
</node>
</node>
<node id="trig_thresh" address="0x8" description="trigger thresholds" fwinfo="endpoint;width=2">
<node id="threshtrig_thresh" address="0x0"/>
<node id="neutrontrig_signal_thresh" address="0x1"/>
<node id="neutrontrig_feature_thresh" address="0x2"/>
<node id="t0" address="0x0">
<node id="thresh" mask="0x3ff">
</node>
<node id="t1" address="0x1">
<node id="pthresh" mask="0x3ff"/>
<node id="cthresh" mask="0x1f0000"/>
<node id="wsize" mask="0xf000000"/>
</node>
<node id="t2" address="0x2">
<node id="pthresh" mask="0x3ff"/>
<node id="cthresh" mask="0x1f0000"/>
<node id="wsize" mask="0xf000000"/>
</node>
</node>
</node>
components/solid/firmware/cfg/sc_chan.dep
View file @ 2680a008
src sc_channels.vhd sc_chan.vhd sc_input_serdes.vhd sc_chan_buf.vhd sc_derand.vhd
#src sc_chan_trig.vhd sc_trig_dummy.vhd sc_npeaks_thresh.vhd sc_npeaks.vhd sc_thresh.vhd
src sc_chan_trig.vhd sc_trig_dummy.vhd
src sc_chan_trig.vhd sc_ctrig_npeaks.vhd sc_ctrig_tot.vhd sc_ctrig_window.vhd sc_ctrig_thresh.vhd
src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd
src -c ipbus-firmware:components/ipbus_slaves ipbus_ported_dpram.vhd
src ipbus_decode_sc_chan.vhd
......
components/solid/firmware/hdl/sc_chan.vhd
View file @ 2680a008
......@@ -43,6 +43,7 @@ entity sc_chan is
rand: in std_logic_vector(13 downto 0);
nzs_en: in std_logic;
zs_en: in std_logic;
mark: in std_logic;
keep: in std_logic;
flush: in std_logic;
err: out std_logic;
......@@ -205,8 +206,6 @@ begin
-- Local triggers
req <= not or_reduce(sctr(BLK_RADIX - 1 downto 0));
ctrig: entity work.sc_chan_trig
generic map(
VAL_WIDTH => 14
......@@ -219,7 +218,7 @@ begin
clk40 => clk40,
rst40 => chan_rst,
d => d_buf,
req => req,
mark => mark,
trig => trig
);
......
components/solid/firmware/hdl/sc_chan_trig.vhd
View file @ 2680a008
......@@ -26,7 +26,7 @@ entity sc_chan_trig is
clk40: in std_logic;
rst40: in std_logic;
d: in std_logic_vector(13 downto 0);
req: in std_logic;
mark: in std_logic;
trig: out std_logic_vector(N_CHAN_TRG - 1 downto 0)
);
......@@ -35,15 +35,10 @@ end sc_chan_trig;
architecture rtl of sc_chan_trig is
signal ctrl: ipb_reg_v(2 downto 0);
signal threshold_trig, threshold_sig, threshold_fe: std_logic_vector(VAL_WIDTH - 1 DOWNTO 0);
begin
threshold_trig <= ctrl(0)(VAL_WIDTH-1 DOWNTO 0);
threshold_sig <= ctrl(1)(VAL_WIDTH-1 DOWNTO 0);
threshold_fe <= ctrl(2)(VAL_WIDTH-1 DOWNTO 0);
reg: entity work.ipbus_ctrlreg_v
reg: entity work.ipbus_ctrlreg_v -- CDC between ctrl (ipb_clk) and (clk40)
generic map(
N_CTRL => 3,
N_STAT => 0
......@@ -56,33 +51,47 @@ begin
q => ctrl
);
trg0: entity work.sc_trig_dummy
trg0: entity work.sc_ctrig_thresh -- direct threshold trigger, delay = 1
generic map(
VAL_WIDTH => VAL_WIDTH
)
port map(
clk => clk40,
rst => rst40,
req => req,
val => d,
threshold => threshold_trig,
clr => mark,
d => d,
threshold => ctrl(0)(VAL_WIDTH - 1 downto 0),
trig => trig(0)
);
-- trg1: entity work.sc_npeaks_thresh
-- generic map(
-- VAL_WIDTH => VAL_WIDTH
-- )
-- port map(
-- clk => clk40,
-- rst => rst40,
-- req => req,
-- d => d,
-- threshold_trig => threshold_sig,
-- threshold_fe => threshold_fe,
-- trig => trig(1)
-- );
trig(1) <= '0';
trg1: entity work.sc_ctrig_npeaks -- peaks-above-threshold trigger, delay = 2
generic map(
VAL_WIDTH => VAL_WIDTH
)
port map(
clk => clk40,
rst => rst40,
clr => mark,
d => d,
cthresh => ctrl(1)(20 downto 16),
wsize => ctrl(1)(27 downto 24),
pthresh => ctrl(1)(VAL_WIDTH - 1 downto 0),
trig => trig(1)
);
trg2: entity work.sc_ctrig_tot -- time-over-threshold trigger, delay = 1
generic map(
VAL_WIDTH => VAL_WIDTH
)
port map(
clk => clk40,
rst => rst40,
clr => mark,
d => d,
cthresh => ctrl(2)(20 downto 16),
wsize => ctrl(2)(27 downto 24),
pthresh => ctrl(2)(VAL_WIDTH - 1 downto 0),
trig => trig(2)
);
end rtl;
components/solid/firmware/hdl/sc_channels.vhd
View file @ 2680a008
......@@ -34,6 +34,7 @@ entity sc_channels is
rand: in std_logic_vector(13 downto 0);
nzs_en: in std_logic;
zs_en: in std_logic;
mark: in std_logic;
keep: in std_logic_vector(N_CHAN - 1 downto 0);
flush: in std_logic_vector(N_CHAN - 1 downto 0);
err: out std_logic;
......@@ -114,6 +115,7 @@ begin
rand => rand,
nzs_en => nzs_en,
zs_en => zs_en,
mark => mark,
keep => keep(i),
flush => flush(i),
err => chan_err(i),
......
components/solid/firmware/hdl/sc_ctrig_npeaks.vhd 0 → 100644
View file @ 2680a008
-- sc_ctrig_npeaks
--
-- Peaks-above-threshold trigger
--
-- Dave Newbold, May 2017
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity sc_ctrig_npeaks is
generic(
VAL_WIDTH: natural;
DELAY: positive := 1
);
port(
clk: in std_logic;
rst: in std_logic;
clr: in std_logic;
d: in std_logic_vector(VAL_WIDTH - 1 downto 0);
cthresh: in std_logic_vector(8 downto 0);
wsize: in std_logic_vector(3 downto 0);
pthresh: in std_logic_vector(VAL_WIDTH - 1 downto 0);
trig: out std_logic
);
end sc_ctrig_npeaks;
architecture rtl of sc_ctrig_npeaks is
signal d1, d2: std_logic_vector(VAL_WIDTH - 1 downto 0);
signal p: std_logic;
signal count: std_logic_vector(cthresh'range);
begin
d1 <= d when rising_edge(clk);
d2 <= d1 when rising_edge(clk);
p <= '1' when unsigned(d1) > unsigned(pthresh) and unsigned(d2) < unsigned(d1) and unsigned(d) <= unsigned(d1) else '0';
count: entity work.sc_ctrig_window
generic map(
C_WIDTH => cthresh'length
)
port map(
clk => clk,
rst => rst,
wsize => wsize,
p => p,
count => count
);
thresh: entity work.sc_ctrig_thresh
generic map(
VAL_WIDTH => cthresh'length
DELAY => 2
)
port map(
clk => clk,
rst => rst,
clr => clr,
d => count,
threshold => cthresh,
trig => trig
);
end rtl;
components/solid/firmware/hdl/sc_ctrig_thresh.vhd 0 → 100644
View file @ 2680a008
-- sc_ctrig_thresh
--
-- Catch values above threshold within a block
--
-- Dave Newbold, April 2017
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity sc_ctrig_thresh is
generic(
VAL_WIDTH: natural;
DELAY: positive := 1
);
port(
clk: in std_logic;
rst: in std_logic;
clr: in std_logic;
d: in std_logic_vector(VAL_WIDTH - 1 downto 0);
threshold: in std_logic_vector(VAL_WIDTH - 1 downto 0);
trig: out std_logic
);
end sc_ctrig_thresh;
architecture rtl of sc_ctrig_thresh is
cdel: std_logic_vector(DELAY - 1 downto 0);
begin
cdel <= cdel(DELAY - 2 downto 0) & clr when rising_edge(clk);
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
trig <= '0';
elsif unsigned(d) > unsigned(threshold) then
trig <= '1';
elsif cdel(DELAY - 1) = '1' then
trig <= '0';
end if;
end if;
end process;
end rtl;
components/solid/firmware/hdl/sc_ctrig_tot.vhd 0 → 100644
View file @ 2680a008
-- sc_ctrig_tot
--
-- Time-over-threshold trigger
--
-- Dave Newbold, May 2017
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity sc_ctrig_tot is
generic(
VAL_WIDTH: natural;
DELAY: positive := 1
);
port(
clk: in std_logic;
rst: in std_logic;
clr: in std_logic;
d: in std_logic_vector(VAL_WIDTH - 1 downto 0);
cthresh: in std_logic_vector(8 downto 0);
wsize: in std_logic_vector(3 downto 0);
pthresh: in std_logic_vector(VAL_WIDTH - 1 downto 0);
trig: out std_logic
);
end sc_ctrig_tot;
architecture rtl of sc_ctrig_tot is
signal p: std_logic;
signal count: std_logic_vector(cthresh'range);
begin
p <= '1' when unsigned(d) > unsigned(pthresh) else '0';
count: entity work.sc_ctrig_window
generic map(
C_WIDTH => cthresh'length
)
port map(
clk => clk,
rst => rst,
wsize => wsize,
p => p,
count => count
);
thresh: entity work.sc_ctrig_thresh
generic map(
VAL_WIDTH => cthresh'length
)
port map(
clk => clk,
rst => rst,
clr => clr,
d => count,
threshold => cthresh,
trig => trig
);
end rtl;
components/solid/firmware/hdl/sc_ctrig_window.vhd 0 → 100644
View file @ 2680a008
-- sc_ctrig_window
--
-- Count features in sliding window
--
-- Dave Newbold, May 2017
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity sc_ctrig_window is
generic(
C_WIDTH: natural
);
port(
clk: in std_logic;
rst: in std_logic;
wsize: in std_logic_vector(3 downto 0);
p: in std_logic;
count: out std_logic_vector(C_WIDTH - 1 downto 0)
);
end sc_ctrig_window;
architecture rtl of sc_ctrig_window is
constant WINDOW_LEN: integer := BLK_RADIX;
signal w, f: std_logic_vector(2 ** wsize'length downto 0);
signal p, r: std_logic;
signal count_i: unsigned(C_WIDTH - 1 downto 0);
begin
w(0) <= p;
dgen: for i in 2 ** wsize'length - 1 downto 0 generate
srl: SRL32CE
port map(
clk => clk,
ce => '1',
a => "11111",
d => w(i),
q31 => w(i + 1)
q => f(i)
);
end generate;
r <= f(to_integer(unsigned(wsize)));
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
count_i <= (others => '0');
else
if p = '1' and r = '0' then
count_i <= count_i + 1;
elsif p = '0' and r = '1' and count_i /= 0 then
count_i <= count_i - 1;
end if;
end if;
end if;
end process;
count <= std_logic_vector(count_i);
end rtl;
components/solid/firmware/hdl/sc_local_trig.vhd
View file @ 2680a008
......@@ -103,8 +103,8 @@ begin
tg1: entity work.sc_trig_gen_or
generic map(
TBIT => 0,
DELAY => 2
TBIT => 0
DELAY => 1
)
port map(
clk => clk40,
......@@ -115,7 +115,7 @@ begin
ack => ta(1)
);
-- Neutron trigger generator
-- peaks-over-threshold trigger generator
tg2: entity work.sc_trig_gen_or
generic map(
......@@ -131,6 +131,22 @@ begin
ack => ta(2)
);
-- time-over-threshold trigger generator
tg3: entity work.sc_trig_gen_or
generic map(
TBIT => 2,
DELAY => 1
)
port map(
clk => clk40,
en => trig_en,
mark => mark,
chan_trig => chan_trig,
valid => tv(3),
ack => ta(3)
);
-- Add more trigger generators here...
-- Priority encoder
......
components/solid/firmware/hdl/sc_ltrig_thresh.vhd 0 → 100644
View file @ 2680a008
-- sc_ctrig_thresh
--
-- Catch values above threshold within a block
--
-- Dave Newbold, April 2017
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity sc_ctrig_thresh is
generic(
VAL_WIDTH: natural
);
port(
clk: in std_logic;
rst: in std_logic;
req: in std_logic;
val: in std_logic_vector(VAL_WIDTH - 1 downto 0);
threshold: in std_logic_vector(VAL_WIDTH - 1 downto 0);
trig: out std_logic
);
end sc_ctrig_thresh;
architecture rtl of sc_ctrig_thresh is
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
trig <= '0';
elsif unsigned(val) > unsigned(threshold) then
trig <= '1';
elsif req = '1' then
trig <= '0';
end if;
end if;
end process;
end rtl;
components/solid/firmware/hdl/sc_trig_gen_or.vhd
View file @ 2680a008
......@@ -24,7 +24,7 @@ entity sc_trig_gen_or is
clk: in std_logic;
en: in std_logic;
mark: in std_logic;
chan_trig: in sc_trig_array;
chan_trig: in sc_trig_array;
valid: out std_logic;
ack: in std_logic
);
......
projects/64chan_test/firmware/hdl/payload.vhd
View file @ 2680a008
......@@ -62,7 +62,7 @@ architecture rtl of payload is
signal sync_ctrl: std_logic_vector(3 downto 0);
signal adc_d: std_logic_vector(63 downto N_CHAN);
signal sctr: std_logic_vector(47 downto 0);
signal trig_en, nzs_en, zs_en, chan_err: std_logic;
signal trig_en, nzs_en, zs_en, chan_err, mark: std_logic;
signal trig_keep, trig_flush, trig_veto: std_logic_vector(N_CHAN - 1 downto 0);
signal chan_trig: sc_trig_array;
signal link_d, link_q: std_logic_vector(15 downto 0);
......@@ -192,6 +192,7 @@ begin
rand => rand(13 downto 0),
nzs_en => nzs_en,
zs_en => zs_en,
mark => mark,
keep => trig_keep,
flush => trig_flush,
err => chan_err,
......@@ -220,6 +221,7 @@ begin
zs_en => zs_en,
sctr => sctr,
rand => rand,
mark => mark,
keep => trig_keep,
flush => trig_flush,
veto => trig_veto,
......
projects/64chan_test/firmware/hdl/top_decl.vhd
View file @ 2680a008
......@@ -11,7 +11,7 @@ package top_decl is
constant MAC_ADDR: std_logic_vector(47 downto 0) := X"020ddba11500"; -- last byte from local addr
constant IP_ADDR: std_logic_vector(31 downto 0) := X"c0a8eb00"; -- last byte from local addr
constant FW_REV: std_logic_vector(15 downto 0) := X"0009";
constant FW_REV: std_logic_vector(15 downto 0) := X"000a";
constant N_CHAN: integer := 64;
constant BLK_RADIX: integer := 8; -- 256 sample blocks
......
projects/8chan_test/firmware/hdl/payload.vhd
View file @ 2680a008
......@@ -74,7 +74,7 @@ architecture rtl of payload is
signal sync_ctrl: std_logic_vector(3 downto 0);
signal adc_d: std_logic_vector(N_CHAN - 1 downto 0);
signal sctr: std_logic_vector(47 downto 0);
signal trig_en, nzs_en, zs_en, chan_err: std_logic;
signal trig_en, nzs_en, zs_en, chan_err, mark: std_logic;
signal trig_keep, trig_flush, trig_veto: std_logic_vector(N_CHAN - 1 downto 0);
signal chan_trig: sc_trig_array;
signal link_d, link_q: std_logic_vector(15 downto 0);
......@@ -216,6 +216,7 @@ begin
rand => rand(13 downto 0),
nzs_en => nzs_en,
zs_en => zs_en,
mark => mark,
keep => trig_keep,
flush => trig_flush,
err => chan_err,
......@@ -244,6 +245,7 @@ begin
zs_en => zs_en,
sctr => sctr,
rand => rand,
mark => mark,
keep => trig_keep,
flush => trig_flush,
veto => trig_veto,
......
projects/8chan_test/firmware/hdl/top_decl.vhd
View file @ 2680a008
......@@ -11,7 +11,7 @@ package top_decl is
constant MAC_ADDR: std_logic_vector(47 downto 0) := X"020ddba11503";
constant IP_ADDR: std_logic_vector(31 downto 0) := X"c0a8eb00";
constant FW_REV: std_logic_vector(15 downto 0) := X"0009";
constant FW_REV: std_logic_vector(15 downto 0) := X"000a";
constant N_CHAN: integer := 8;
constant BLK_RADIX: integer := 8; -- 256 sample blocks
......
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