Commit 1b36f4f1 authored by Dave Newbold's avatar Dave Newbold

Updating sim code

parent ad38198b
src sc_daq.vhd
src ipbus_decode_sc_daq.vhd
addrtab -t sc_daq.xml
src sc_rtrig.vhd
include sc_timing_sim.dep sc_fake.dep sc_chan.dep sc_trig.dep sc_trig_link.dep sc_roc.dep
include sc_timing_sim.dep sc_fake.dep sc_chan.dep sc_trig.dep sc_trig_link.dep sc_roc.dep sc_rtrig.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
......@@ -116,7 +116,7 @@ begin
ctrl_src <= ctrl(0)(7 downto 6);
slip <= sync_ctrl(0) and ctrl_en_sync; -- CDC
chan_rst <= (sync_ctrl(1) and ctrl_en_sync) or rst40; -- CDC
chan_rst <= (sync_ctrl(1) and ctrl_en_sync) or rst40; -- CDC (this might go away soon)
cap <= sync_ctrl(2) and ctrl_en_sync; -- CDC
inc <= sync_ctrl(3) and ctrl_en_sync; -- CDC
......
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