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euro-adc-65m-14b-40cha-gw
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euro-adc-65m-14b-40cha
euro-adc-65m-14b-40cha-gw
Commits
1b36f4f1
Commit
1b36f4f1
authored
Aug 25, 2017
by
Dave Newbold
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Updating sim code
parent
ad38198b
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2 changed files
with
2 additions
and
3 deletions
+2
-3
sc_daq_sim.dep
components/solid/firmware/cfg/sc_daq_sim.dep
+1
-2
sc_chan.vhd
components/solid/firmware/hdl/sc_chan.vhd
+1
-1
No files found.
components/solid/firmware/cfg/sc_daq_sim.dep
View file @
1b36f4f1
src sc_daq.vhd
src ipbus_decode_sc_daq.vhd
addrtab -t sc_daq.xml
src sc_rtrig.vhd
include sc_timing_sim.dep sc_fake.dep sc_chan.dep sc_trig.dep sc_trig_link.dep sc_roc.dep
include sc_timing_sim.dep sc_fake.dep sc_chan.dep sc_trig.dep sc_trig_link.dep sc_roc.dep sc_rtrig.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
components/solid/firmware/hdl/sc_chan.vhd
View file @
1b36f4f1
...
...
@@ -116,7 +116,7 @@ begin
ctrl_src
<=
ctrl
(
0
)(
7
downto
6
);
slip
<=
sync_ctrl
(
0
)
and
ctrl_en_sync
;
-- CDC
chan_rst
<=
(
sync_ctrl
(
1
)
and
ctrl_en_sync
)
or
rst40
;
-- CDC
chan_rst
<=
(
sync_ctrl
(
1
)
and
ctrl_en_sync
)
or
rst40
;
-- CDC
(this might go away soon)
cap
<=
sync_ctrl
(
2
)
and
ctrl_en_sync
;
-- CDC
inc
<=
sync_ctrl
(
3
)
and
ctrl_en_sync
;
-- CDC
...
...
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