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euro-adc-65m-14b-40cha-gw
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euro-adc-65m-14b-40cha
euro-adc-65m-14b-40cha-gw
Commits
19de6702
Commit
19de6702
authored
Apr 20, 2018
by
Dave Newbold
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Adjusting timestamp counters
parent
acdd6b29
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sc_trig_ro_block.vhd
components/solid/firmware/hdl/sc_trig_ro_block.vhd
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components/solid/firmware/hdl/sc_trig_ro_block.vhd
View file @
19de6702
...
...
@@ -37,7 +37,7 @@ architecture rtl of sc_trig_ro_block is
signal
tctr_i
:
unsigned
(
27
downto
0
);
signal
go
,
blkend
:
std_logic
;
signal
chen
,
keep_c
:
std_logic_vector
(
63
downto
0
);
signal
bctr
:
unsigned
(
47
-
BLK_RADIX
downto
0
);
signal
bctr
:
unsigned
(
31
-
BLK_RADIX
downto
0
);
begin
...
...
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